Power
Supplies
9
7
5
3
1
10
8
6
4
2
FPGA1_SPI_MOSI
FPGA1_SPI_SCLK
FPGA1_FLASH_SPI_CSN
FPGA1_SPI_CSN (not used)
FPGA1_VCCIO
GND (not used)
FPGA1_CDONE (not used)
FPGA1_CRESETN
FPGA1_SPI_MISO
GND
Cascade Radar Host Board
FPGA Programming Header
Top-Down View. Reference
layout/assembly drawing for pin
orientation/positions.
VCC
ispEN/PROG
TCK/SCLK
TDI/SI
TRST
TDO/SO
GND
Lattice HW-USBN-2B
Programming Cable
Leads
Cascade Radar Host Board to
FPGA Programmer Hookup
For FPGA Flash Programming
DONE
Hardware Specifications
16
SPRUIS6 – September 2019
Copyright © 2019, Texas Instruments Incorporated
MMWCAS-DSP-EVM
2.5.3
Ethernet Jack (J12)
The MMWCAS-DSP-EVM supports a Gigabit Ethernet port to provide the connection to the network. The
Ethernet port is interfaced to the TDA2 through the Ethernet PHY DP83867, and is used to stream the
captured data over the network to the host PC.
The DP83867 device is a robust, low power, fully featured physical layer transceiver with integrated PMD
sublayers to support 10BASE-Te, 100BASE-TX, and 1000BASE-T Ethernet protocols. Optimized for ESD
protection, the DP83867 exceeds 8-kV IEC 61000-4-2(direct contact)
The DP83867 provides precision clock synchronization, including a synchronous Ethernet clock output. It
has low latency and provides IEEE 1588 Start of Frame Detection.
2.5.4
PCIe m.2 socket(m-keyed) (J14)
The DSP EVM supports PCIe 2.0 through an m.2 connector. Out of the box, a 512 GB SSD is assembled
on the EVM. The connector is a JAE Electronics SM3ZS067U410AMR1000 PCI express m.2 connector.
The SSD drive provides 3.3 V through the connector, and the data lanes have been length and
impedance matched through the PCIE spec document. The EVM has a notch with a small standoff that
allows a size 2280 SSD card to be securely attached with the provided machine screw. The
recommended SSD is a single-sided card, but a double-sided card can be used if the SSD components do
not touch the board components, due to height.
2.5.5
Lattice FPGA Headers (J3,J5,J7,J9)
The EVM contains four programming headers for the on board FPGA and flash devices. Out of the box,
the FPGAs are flashed so they are ready to use. If the FPGAs must be flashed, refer to
for
proper cable assembly. Lattice Diamond 3.10 (not included) and Lattice HW-USBN-2B Programmer (not
included) must be used. Along with each FPGA, there is a small NOR flash device used to hold the image
on power cycle.
Figure 9. FPGA Flash Programming Header Pinout