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Table of Contents

1 First-Time Setup

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3

1.1 Evaluation Module Contents..............................................................................................................................................

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1.2 Evaluation Setup Requirements.........................................................................................................................................

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2 EVM Connections

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4

2.1 Connection Diagram..........................................................................................................................................................

4

2.2 Power Supply.....................................................................................................................................................................

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2.3 Reference Clock.................................................................................................................................................................

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2.4 Output Connections...........................................................................................................................................................

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2.5 Programming Interface.......................................................................................................................................................

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3 Feature Evaluation

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8

3.1 Buffer, Divider, and Multiplier Modes..................................................................................................................................

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3.2 SYSREF Generation........................................................................................................................................................

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3.3 SYSREF Delay Generators..............................................................................................................................................

13

4 Schematic

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14

5 PCB Layout and Layer Stack-Up

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5.1 PCB Layer Stack-Up........................................................................................................................................................

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5.2 PCB Layout......................................................................................................................................................................

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6 Bill of Materials

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A Troubleshooting

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B USB2ANY Firmware Upgrade

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25

Table of Contents

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2

LMX1204EVM User's Guide

SNAU266 – JULY 2021

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Copyright © 2021 Texas Instruments Incorporated

Summary of Contents for LMX1204EVM

Page 1: ...d divide outputs by up to 8 GHz A separate auxiliary clock divider can be used for FPGAs or other logic ICs Each RF output and the logic clock is paired with a complementary SYSREF output with picosecond precision delay tuning capability and can be operated as a generator with synchronization capability across multiple devices or as a repeater The device runs from a single 2 5 V supply and is prog...

Page 2: ...rface 5 3 Feature Evaluation 8 3 1 Buffer Divider and Multiplier Modes 8 3 2 SYSREF Generation 11 3 3 SYSREF Delay Generators 13 4 Schematic 14 5 PCB Layout and Layer Stack Up 16 5 1 PCB Layer Stack Up 16 5 2 PCB Layout 17 6 Bill of Materials 21 A Troubleshooting 23 B USB2ANY Firmware Upgrade 25 Table of Contents www ti com 2 LMX1204EVM User s Guide SNAU266 JULY 2021 Submit Document Feedback Copyr...

Page 3: ...Texas Instruments Clocks and Synthesizers TICS Pro software Full evaluation requires the following additional hardware A high speed 4 CH oscilloscope capable of resolving 5 ps step size for SYSREF delay tuning A 2 CH arbitrary function generator or other pulse source capable of outputting complementary LVDS pulses and DC levels 1 25 V 0 2 V differential into 100 Ω DC load for triggering SYSREF SYN...

Page 4: ... range during operation 2 3 Reference Clock Connect the CLKINP SMA connector to a high quality signal source such as an SMA100B signal generator Both CLKIN inputs are terminated internally with 50 Ω to AC GND that is GND connection is formed by an internal capacitor so no external termination is required or recommended The other CLKINN SMA connector may be optionally installed beforehand so the in...

Page 5: ...l DC block is not required The unused CLKOUT SMA connector must be terminated with a 50 Ω load or a differential connection may be used if a balun with a suitable frequency range is available If additional hardware such as a high speed oscilloscope and phase noise analyzer are available they may also be connected to the output SMA connectors Recommended oscilloscope connections include one CLKOUT ...

Page 6: ...ontroller is selected To confirm controller selection click the Identify button to blink the onboard green communications LED several times in rapid succession the LED will return to solid green once completed After confirming the USB2ANY connection close the interface window EVM Connections www ti com 6 LMX1204EVM User s Guide SNAU266 JULY 2021 Submit Document Feedback Copyright 2021 Texas Instru...

Page 7: ...re that the main window now shows the USB2ANY connection over SPI www ti com EVM Connections SNAU266 JULY 2021 Submit Document Feedback LMX1204EVM User s Guide 7 Copyright 2021 Texas Instruments Incorporated ...

Page 8: ...pplied on all output pins manually disable the unused outputs using the CHx_EN fields to completely power down unused channels or the CLKOUTx_EN SYSOUTx_EN and LOGICLK_EN LOGISYS_EN fields to power down output buffers only Powering down unused channels greatly reduces current consumption and for the logic clocks in particular can reduce spurious interference After the profile is loaded and any cha...

Page 9: ...eanly enters each mode first the desired configuration should be prepared in the GUI then from the User Controls page the device should be reset by toggling the RESET field and finally the registers should be reloaded using the USB Communications Write All Registers menu option or by pressing the accelerator keys CTRL L www ti com Feature Evaluation SNAU266 JULY 2021 Submit Document Feedback LMX12...

Page 10: ...gure 3 3 3200 MHz Multiplier x4 Mode Signal Analyzer Plot Feature Evaluation www ti com 10 LMX1204EVM User s Guide SNAU266 JULY 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated ...

Page 11: ...ate condition Continuous Pulser or Repeater In generator modes continuous or pulser FINTERPOLATOR FSYSREF 0 must be ensured SYSREF_DLY_BYP field must be configured appropriately for generator or repeater modes a GUI autoset condition normally ensures this whenever SYSREF_MODE is set SRREQ_VCM field should be set to DC coupled mode for continuous or pulsed generator output In repeater mode output t...

Page 12: ...frequency consequently the SYSREF generator still matches to the falling edge of the clock input even for multiplier and divider modes Figure 3 6 3200 MHz Multiplier Mode With CLKOUT LOGICLK and SYSREF Feature Evaluation www ti com 12 LMX1204EVM User s Guide SNAU266 JULY 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated ...

Page 13: ...st of the CLKIN frequency range Each channel has its own delay codes which can be entered The delay code algorithm is documented in the data sheet To simplify delay calculation the GUI provides an estimated relative delay enter the relative delay and the GUI will calculate the correct step values to achieve the requested delay as closely as possible Alternately the register based delay fields can ...

Page 14: ...4 Schematic Figure 4 1 Schematic LMX1204 Schematic www ti com 14 LMX1204EVM User s Guide SNAU266 JULY 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated ...

Page 15: ...Figure 4 2 Schematic USB2ANY www ti com Schematic SNAU266 JULY 2021 Submit Document Feedback LMX1204EVM User s Guide 15 Copyright 2021 Texas Instruments Incorporated ...

Page 16: ... layer RO4350B Er 3 66 RF GND layer FR4 Er 4 2 FR4 Er 4 2 Bottom layer 62 mil Signal GND layer 10 mil Figure 5 1 PCB Layer Stack Up PCB Layout and Layer Stack Up www ti com 16 LMX1204EVM User s Guide SNAU266 JULY 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated ...

Page 17: ... PCB Layout Figure 5 2 PCB Layer Plot Top Layer www ti com PCB Layout and Layer Stack Up SNAU266 JULY 2021 Submit Document Feedback LMX1204EVM User s Guide 17 Copyright 2021 Texas Instruments Incorporated ...

Page 18: ...Figure 5 3 PCB Layer Plot Layer 2 RF GND PCB Layout and Layer Stack Up www ti com 18 LMX1204EVM User s Guide SNAU266 JULY 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated ...

Page 19: ...Figure 5 4 PCB Layer Plot Layer 3 Signal GND www ti com PCB Layout and Layer Stack Up SNAU266 JULY 2021 Submit Document Feedback LMX1204EVM User s Guide 19 Copyright 2021 Texas Instruments Incorporated ...

Page 20: ...Figure 5 5 PCB Layer Plot Bottom Layer PCB Layout and Layer Stack Up www ti com 20 LMX1204EVM User s Guide SNAU266 JULY 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated ...

Page 21: ...J25 J26 23 CONN SMA JACK STR EDGE MNT CON SMA EDGE S RF Solutions Ltd J27 1 Header 100mil 2x1 Gold TH TSW 102 07 G S Samtec L1 L2 L3 L4 4 Ferrite Bead 120 Ω 100 MHz 3 A 0603 BLM18SG121TN1D MuRata Q1 1 MOSFET N CH 50 V 0 22 A SOT 23 BSS138 Fairchild Semiconductor R1 1 RES 180 5 0 1 W AEC Q200 Grade 0 0603 CRCW0603180RJN EA Vishay Dale R2 R3 R9 R24 4 RES 0 5 0 1 W AEC Q200 Grade 0 0603 CRCW06030000Z...

Page 22: ...5001 Keystone U1 1 12 8 GHz SYSREF Buffer Multiplier Divider LMX1204RHAT Texas Instruments U2 1 25 MHz Mixed Signal Microcontroller MSP430F5529IPN Texas Instruments U3 1 4 Channel ESD Protection Array TPD4E004DRYR Texas Instruments U4 1 150mA Linear Regulator 3 3V LP5900SDX 3 3 NOPB Texas Instruments Y1 1 Crystal 24 000 MHz 20pF SMD ECS 240 20 5PX TR ECS Inc Bill of Materials www ti com 22 LMX1204...

Page 23: ...terface pop up using the identify button Ensure all registers have been loaded Ctrl L and that the device current has changed proportional to the number of functional blocks enabled in the device If a communication issue with the device is suspected try toggling the POWERDOWN bit from the User Controls page and observe the EVM current Note that the first write to R0 after POR will be ignored If th...

Page 24: ...nnel CHx_EN LOGIC_EN and the SYSREF buffer SYSOUTx_EN LOGISYS_EN are enabled Confirm that Windowing mode is not enabled on the User Controls page SYSWND_EN 0 Confirm that R15 9 1 This should be set automatically by the GUI so this potential root cause should be rare Confirm the 1 1 V and 1 5 V source for SYSREFREQ_N and SYSREFREQ_P respectively are actually resulting in the required voltages at th...

Page 25: ... the update 1 When the USB2ANY Firmware Requirement pop up window appears click OK to continue Figure B 1 Firmware Requirement 2 The Figure B 2 pop up window will load Disconnect the USB cable from the EVM Figure B 2 Firmware Loader 3 While pressing the BSL button shown below connect the USB2ANY cable Figure B 3 BSL Button Location www ti com USB2ANY Firmware Upgrade SNAU266 JULY 2021 Submit Docum...

Page 26: ...ear Figure B 4 Update Firmware 5 Click Upgrade Firmware to start the firmware upgrade Click Close after the upgrade is complete Figure B 5 Firmware Update Complete USB2ANY Firmware Upgrade www ti com 26 LMX1204EVM User s Guide SNAU266 JULY 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated ...

Page 27: ...ware to check the USB connection Make sure the USB Connected button is green Figure B 6 USB Communications www ti com USB2ANY Firmware Upgrade SNAU266 JULY 2021 Submit Document Feedback LMX1204EVM User s Guide 27 Copyright 2021 Texas Instruments Incorporated ...

Page 28: ...other than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control techniques are used to the extent TI deems necessary TI does not test all parameters of each EVM User s claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects...

Page 29: ... These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation...

Page 30: ...y for convenience and should be verified by User 1 Use EVMs in a shielded room or any other test facility as defined in the notification 173 issued by Ministry of Internal Affairs and Communications on March 28 2006 based on Sub section 1 1 of Article 6 of the Ministry s Rule for Enforcement of Radio Law of Japan 2 Use EVMs only after User obtains the license of Test Radio Station as provided in R...

Page 31: ... any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees affiliates contractors or designees 4 4 User assumes all...

Page 32: ...OR DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthermore no return of EVM s will be accepted if the package has been opened and no return of the EVM s will be accepted if they are damaged or otherwise not in a resalable condition If User feels it has...

Page 33: ...s are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you wi...

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