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4 Power-Supply Connections

Connect the power-supply source and ground to the terminal block labeled 

J1 

as shown in 

Figure 4-1

.

Alternatively, connect the power-supply source to 

TP1

, and connect the ground of the power-supply 

TP2

.

Decoupling capacitors and a ferrite bead isolate the EVM power from the LMK1C1104 device power pins.

TP1 and TP2:

 

Connect VDD to TP1 
Connect GND to TP2

J1 
Terminal 
Block

Figure 4-1. Power Supply Connection Locations

The LMK1C1104EVM operates from a single 3.3-V / 2.5-V / 1.8-V supply.

5 Enabling/Disabling the Outputs

The enable pin, 1G, of the LMK1C1104 can be controlled using jumper 

J3

. Pull 1G to VDD by shunting pins 2

and 3 of J3 to enable the outputs as shown in 

Figure 5-1

. Leave 1G floating or pull to GND to disable the

outputs.

J3:

 

Shunt pins 2 (1G) and 
3 (VDD) to enable the 
outputs

Figure 5-1. J3 Jumper Location

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Power-Supply Connections

SNAU249A – DECEMBER 2019 – REVISED DECEMBER 2020

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LMK1C1104 Low-Additive, Phase-Noise LVCMOS Clock Buffer Evaluation

Board

3

Copyright © 2020 Texas Instruments Incorporated

Summary of Contents for LMK1C1104

Page 1: ... the electrical performance of the LMK1C1104 Throughout this document the acronym EVM and the phrases evaluation module and evaluation board are synonymous with the LMK1C1104EVM Figure 8 1 illustrates the LMK1C1104EVM The LMK1C1104EVM is equipped with 50 Ω SMA connectors and impedance controlled 50 Ω microstrip transmission lines for best performance www ti com SNAU249A DECEMBER 2019 REVISED DECEM...

Page 2: ... V supply Clock output traces are length matched 2 Signal Path and Control Circuitry The LMK1C1104EVM supports single ended inputs up to 250 MHz For more information about the LMK1C1104 see the LMK1C1104 product data sheet available for download from the TI Web site www ti com 3 Getting Started The LMK1C1104EVM has self explanatory labeling and uses similar naming conventions as the LMK1C1104 prod...

Page 3: ...Locations The LMK1C1104EVM operates from a single 3 3 V 2 5 V 1 8 V supply 5 Enabling Disabling the Outputs The enable pin 1G of the LMK1C1104 can be controlled using jumper J3 Pull 1G to VDD by shunting pins 2 and 3 of J3 to enable the outputs as shown in Figure 5 1 Leave 1G floating or pull to GND to disable the outputs J3 Shunt pins 2 1G and 3 VDD to enable the outputs Figure 5 1 J3 Jumper Loca...

Page 4: ...al Block 2 Circuits 039544 3002 Lead 7439 92 1 Table 7 2 Bill of Materials DESIGNATOR QTY VALUE PACKAGE REFERENCE PART NUMBER MANUFACTURER C1 1 10uF 0805 C0805C106K8PACTU Kemet C2 1 1uF 0603 C0603X105J8RAC7867 Kemet C3 C4 C5 3 0 1uF 0402 C0402C104K8RACAUTO Kemet H1 H2 H3 H4 4 4 40 0 25 Screw NY PMS 440 0025 PH B F Fastener Supply H5 H6 H7 H8 4 0 5 Standoff 1902C Keystone J1 1 Terminal Block TH 039...

Page 5: ... 1 2 3 4 5 J4 1 2 3 4 5 J5 1 2 3 4 5 J8 1 2 3 4 5 J9 GND VDD Y0 Y1 Y2 Y3 Y0 Y1 Y2 Y3 100 R1 100 R3 GND VDD 1 2 3 J3 GND VDD 0 R4 GND 0 R2 CLKIN 1G 1 2 3 4 5 J2 CLKIN 1 1G 2 Y0 3 GND 4 Y2 5 VDD 6 Y3 7 Y1 8 LMK1C1104PW U1 Place decoupling caps close to device Figure 8 1 LMK1C1104 Schematic www ti com Schematic SNAU249A DECEMBER 2019 REVISED DECEMBER 2020 Submit Document Feedback LMK1C1104 Low Additi...

Page 6: ...igures and cross references throughout the document 1 Removed 1 5 V supply option 2 Added Figure 4 1 3 Added Figure 5 1 3 Added content to the Output Clock section 4 Changed Table 7 2 4 Changed Figure 8 1 5 Revision History www ti com 6 LMK1C1104 Low Additive Phase Noise LVCMOS Clock Buffer Evaluation Board SNAU249A DECEMBER 2019 REVISED DECEMBER 2020 Submit Document Feedback Copyright 2020 Texas ...

Page 7: ...other than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control techniques are used to the extent TI deems necessary TI does not test all parameters of each EVM User s claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects...

Page 8: ... These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation...

Page 9: ...y for convenience and should be verified by User 1 Use EVMs in a shielded room or any other test facility as defined in the notification 173 issued by Ministry of Internal Affairs and Communications on March 28 2006 based on Sub section 1 1 of Article 6 of the Ministry s Rule for Enforcement of Radio Law of Japan 2 Use EVMs only after User obtains the license of Test Radio Station as provided in R...

Page 10: ... any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees affiliates contractors or designees 4 4 User assumes all...

Page 11: ...OR DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthermore no return of EVM s will be accepted if the package has been opened and no return of the EVM s will be accepted if they are damaged or otherwise not in a resalable condition If User feels it has...

Page 12: ...se resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for...

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