Texas Instruments LMK05318B EVM, Manual

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EVM Configuration
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6 SNAU253 – June 2020
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LMK05318B EVM User's Guide
(1)
When HW_SW_CTRL = Float, STATUS[1:0] pins must not be pulled high or low externally during POR to ensure proper start-up
into SPI Mode.
Table 4. Logic Pin Descriptions - SPI Mode (HW_SW_CTRL = Float)
PIN NAME (TYPE) DESCRIPTION
GPIO1/SCS
(2-level input)
SPI Chip Select (SCS)
See Table 2 .
GPIO2/SDO/FINC
(2-level input)
SPI Data Out (SDO / SOMI)
See Table 2
STATUS0,
STATUS1
(Logic outputs)
Status Outputs
Each STATUS pin is a programmable status output that supports NMOS open-drain or 3.3-V LVCMOS
driver type. The output states of STATUS0 and STATUS1 are shown on active-high LEDs D4 and D5,
respectively.
(1)
(1)
In ROM + I
2
C Mode, the two I
2
C address LSBs are forced to 00b (address = 0x64h).
Table 5. Logic Pin Descriptions - ROM + I
2
C Mode (HW_SW_CTRL = 1)
(1)
PIN NAME (TYPE) DESCRIPTION
GPIO[2:0]
(2-level inputs)
GPIO[2:0] Function at POR: ROM Page Selection
GPIO[2:0] pins are sampled on POR to select the ROM page settings used to initialize the registers.
The GPIO[2:0] pins are controlled by J5, J8 and J7, respectively.
GPIO2 Function after POR: DPLL DCO Mode Frequency Increment (FINC)
After POR, the GPIO2 pin can be operated as an FINC input in the same way described for I
2
C
mode (see the GPIO2/FINC description in Table 3 ).
GPIO[2:0] STATES ROM PAGE SELECT
000b (Default) ROM Page 0
001b ROM Page 1
010b ROM Page 2
... ...
110b ROM Page 6
111b ROM Page 7
STATUS0,
STATUS1/FDEC
(Logic outputs)
Status Outputs
Each STATUS pin is a programmable status output that supports NMOS open-drain or 3.3-V LVCMOS
driver type. The output states of STATUS0 and STATUS1 are shown on active-high LEDs D4 and D5,
respectively.
DPLL DCO Mode Frequency Decrement (FDEC)
After POR, the STATUS1 pin can be operated as an FDEC input in the same way described in Table 3 .