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SNAU253 – June 2020

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Copyright © 2020, Texas Instruments Incorporated

LMK05318B EVM User's Guide

Figure 14. Layer 4 - Power Routing

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Summary of Contents for LMK05318B EVM

Page 1: ...perty of their respective owners 3 Features LMK05318B DUT DPLL with programmable loop bandwidth for input jitter and wander attenuation Two Analog PLLs APLLs for flexible low jitter clock generation Two clock inputs supporting hitless switching and holdover Eight differential clock outputs or combination of differential and up to eight LVCMOS clocks On chip EEPROM for custom start up clocks SMA po...

Page 2: ...W_CTRL Tie pin 03 J7 GPIO0 SYNCN Tie pin 01 J8 GPIO1 SCS Tie pin 02 J5 GPIO2 SOMI Tie pin 02 J10 VDD Tie pins 1 2 This jumper decides whether the VDD pins are supplied by onboard LDO or external power supply Short pins 1 2 VDD is supplied by LDO Short pins 2 3 VDD is supplied by VIN1 external power supply J11 VDDO Tie pins 1 2 This jumper decides whether the VDDO pins are supplied by onboard LDO o...

Page 3: ...umentation Feedback Copyright 2020 Texas Instruments Incorporated LMK05318B EVM User s Guide Figure 1 LMK05318B EVM with Default Jumper Settings 2 Device Start Up Modes The LMK05318B can start up in one of three modes depending on the 3 level input level sampled on the HW_SW_CTRL pin upon power on reset POR The start up modes are listed in Table 2 ...

Page 4: ...bit slave address of 0x64 Logic pins SDA SDI SCL SCK I2 C Data I2 C Clock GPIO 2 0 ROM page select at POR After POR GPIO2 SDO FINC and STATUS1 FDEC pins can function the same as for HW_SW_CTRL 0 if enabled by registers To select this mode short pin 03 of J3 Configure jumpers J7 J8 and J5 to set voltage levels of GPIO0 GPIO1 and GPIO2 NOTE To ensure proper start up into EEPROM SPI Mode the HW_SW_CT...

Page 5: ...upper 5 bits of the I2 C address are initialized from EEPROM SLAVEADR 7 3 11001b GPIO1 STATE J8 7 BIT SLAVE ADDRESS 0 Default Tie pin 03 1100100b 0x64h Float Leave all pins open 1100101b 0x65h 1 Tie pin 01 1100111b 0x66h GPIO2 SDO FINC 2 level input DPLL DCO Mode Frequency Increment FINC When DCO mode and GPIO pin control are enabled by registers a high pulse on the FINC input will increment the D...

Page 6: ...able 5 Logic Pin Descriptions ROM I2 C Mode HW_SW_CTRL 1 1 PIN NAME TYPE DESCRIPTION GPIO 2 0 2 level inputs GPIO 2 0 Function at POR ROM Page Selection GPIO 2 0 pins are sampled on POR to select the ROM page settings used to initialize the registers The GPIO 2 0 pins are controlled by J5 J8 and J7 respectively GPIO2 Function after POR DPLL DCO Mode Frequency Increment FINC After POR the GPIO2 pin...

Page 7: ...www ti com EVM Schematics 7 SNAU253 June 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated LMK05318B EVM User s Guide 4 EVM Schematics Figure 2 Schematic 1 Power Supply ...

Page 8: ...EVM Schematics www ti com 8 SNAU253 June 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated LMK05318B EVM User s Guide Figure 3 Schematic 2 Power Distribution ...

Page 9: ...ww ti com EVM Schematics 9 SNAU253 June 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated LMK05318B EVM User s Guide Figure 4 Schematic 3 LMK05318B and XO Input Interfaces ...

Page 10: ...EVM Schematics www ti com 10 SNAU253 June 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated LMK05318B EVM User s Guide Figure 5 Schematic 4 Clock Input Interfaces ...

Page 11: ... ti com EVM Schematics 11 SNAU253 June 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated LMK05318B EVM User s Guide Figure 6 Schematic 5 Clock Output Interfaces OUT0 to OUT3 ...

Page 12: ...EVM Schematics www ti com 12 SNAU253 June 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated LMK05318B EVM User s Guide Figure 7 Schematic 6 Clock Outputs OUT4 to OUT7 ...

Page 13: ...www ti com EVM Schematics 13 SNAU253 June 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated LMK05318B EVM User s Guide Figure 8 Schematic 7 Logic I O Interfaces ...

Page 14: ...VM Schematics www ti com 14 SNAU253 June 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated LMK05318B EVM User s Guide Figure 9 Schematic 8 USB MCU and I2 C SPI Jumper Block ...

Page 15: ...www ti com EVM Schematics 15 SNAU253 June 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated LMK05318B EVM User s Guide Figure 10 Schematic 9 Hardware ...

Page 16: ...EVM Layouts www ti com 16 SNAU253 June 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated LMK05318B EVM User s Guide 5 EVM Layouts Figure 11 Top Layer Composite View ...

Page 17: ...www ti com EVM Layouts 17 SNAU253 June 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated LMK05318B EVM User s Guide Figure 12 Layer 2 Ground Plane ...

Page 18: ...EVM Layouts www ti com 18 SNAU253 June 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated LMK05318B EVM User s Guide Figure 13 Layer 3 Signal Routing ...

Page 19: ...www ti com EVM Layouts 19 SNAU253 June 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated LMK05318B EVM User s Guide Figure 14 Layer 4 Power Routing ...

Page 20: ...EVM Layouts www ti com 20 SNAU253 June 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated LMK05318B EVM User s Guide Figure 15 Layer 5 Ground Plane ...

Page 21: ...www ti com EVM Layouts 21 SNAU253 June 2020 Submit Documentation Feedback Copyright 2020 Texas Instruments Incorporated LMK05318B EVM User s Guide Figure 16 Bottom Layer Composite View ...

Page 22: ...36 C37 C40 C41 C43 C66 C73 C75 C85 C86 C92 C93 C95 22 10 µF CAP CERM 10 µF 10 V 20 X5R 0603 0603 C1608X5R1A10 6M080AC TDK C44 1 0 1 µF CAP CERM 0 1 µF 50 V 10 X7R 0603 0603 06035C104KAT2 A AVX C56 C57 2 33 pF CAP CERM 33 pF 50 V 5 C0G NP0 0402 0402 GRM1555C1H33 0JA01D MuRata C60 1 0 01 µF CAP CERM 0 01 µF 50 V 5 X7R 0603 0603 C0603C103J5R ACTU Kemet C61 C74 2 30 pF CAP CERM 30 pF 50 V 5 C0G NP0 06...

Page 23: ...Bead 220 Ω 100 MHz 2 5 A 0603 0603 BLM18SG221TN 1D MuRata FB13 1 300 Ω Ferrite Bead 300 Ω 100 MHz 0 4 A 1 6x0 8x0 95 mm 1 6x0 8x0 95 mm LI0603D301R 10 Laird Signal Integrity Products H1 H2 H3 H4 H5 H6 6 Machine Screw Round 4 40 x 1 4 Nylon Philips panhead Screw NY PMS 440 0025 PH B and F Fastener Supply H7 H8 H9 H10 H11 H12 6 Standoff Hex 0 5 in L 4 40 Nylon Standoff 1902C Keystone J1 1 Connector ...

Page 24: ... JNEA Vishay Dale R14 R17 R18 R19 R22 R24 R27 R37 R38 R39 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 R69 R70 R71 R72 R73 R74 R92 R96 R97 R98 R99 R100 R101 R103 R104 R113 R114 R116 R117 R130 R162 58 0 RES 0 5 0 063 W AEC Q200 Grade 0 0402 0402 CRCW04020000 Z0ED Vishay Dale R40 1 240 RES 240 5 0 063 W 0402 0402 CRCW0402240 RJNED Vishay...

Page 25: ...2 1 0 k RES 1 0 k 5 0 1 W AEC Q200 Grade 0 0603 0603 CRCW06031K00 JNEA Vishay Dale R125 R126 R129 R161 4 470 RES 470 5 0 063 W AEC Q200 Grade 0 0402 0402 CRCW0402470 RJNED Vishay Dale R131 R132 2 33 RES 33 5 0 063 W AEC Q200 Grade 0 0402 0402 CRCW040233R 0JNED Vishay Dale R133 1 1 5 k RES 1 5 k 5 0 063 W AEC Q200 Grade 0 0402 0402 CRCW04021K50 JNED Vishay Dale R134 1 1 2 Meg RES 1 2 M 5 0 1 W AEC ...

Page 26: ...ith Two Frequency Domains VQFN48 LMK05318B Texas Instruments U2 1 4 Channel ESD Protection Array for High Speed Data Interfaces DRY0006A USON 6 DRY0006A TPD4E004DRY R Texas Instruments U3 1 150 mA Ultra Low Noise LDO for RF and Analog Circuits Requires No Bypass Capacitor NGF0006A WSON 6 NGF0006A LP5900SD 3 3 NOPB Texas Instruments U4 1 Single 2 Input Exclusive OR Gate DBV0005A LARGE T and R DBV00...

Page 27: ...6 V 10 X7R 0201 0201 GRM033R71C10 1KA01D MuRata C58 C59 0 100 pF CAP CERM 100 pF 50 V 5 C0G NP0 0603 0603 06035A101JAT2 A AVX C68 C103 0 10 µF CAP CERM 10 µF 25 V 20 X5R 1206 1206 GRM31CR61E1 06MA12L MuRata C72 C105 0 47 µF CAP CERM 47 µF 10 V 20 X5R 0805 0805 GRM21BR61A4 76ME15L MuRata FID1 FID2 FID3 FID4 FID5 FID6 0 Fiducial mark There is nothing to buy or mount N A N A N A J14 J16 J19 J20 J21 J...

Page 28: ...acturer R109 R110 0 1 5 k RES 1 5 k 5 0 1 W AEC Q200 Grade 0 0603 0603 CRCW06031K50 JNEA Vishay Dale R127 0 10 0 k RES 10 0 k 1 0 063 W 0402 0402 CRCW040210K0 FKED Vishay Dale R146 0 1 00 k RES 1 00 k 1 0 063 W 0402 0402 CRCW04021K00 FKED Vishay Dale Y2 0 10 MHz TCXO CMOS Oscillator 3 3 V 4 SMD No Lead SMT4_5MM0_3 MM2 TWETMCJANF 10 000000 Taitien 7 References TICS Pro Software GUI Texas Instrument...

Page 29: ...other than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control techniques are used to the extent TI deems necessary TI does not test all parameters of each EVM User s claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects...

Page 30: ... These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation...

Page 31: ...y for convenience and should be verified by User 1 Use EVMs in a shielded room or any other test facility as defined in the notification 173 issued by Ministry of Internal Affairs and Communications on March 28 2006 based on Sub section 1 1 of Article 6 of the Ministry s Rule for Enforcement of Radio Law of Japan 2 Use EVMs only after User obtains the license of Test Radio Station as provided in R...

Page 32: ... any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees affiliates contractors or designees 4 4 User assumes all...

Page 33: ...OR DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthermore no return of EVM s will be accepted if the package has been opened and no return of the EVM s will be accepted if they are damaged or otherwise not in a resalable condition If User feels it has...

Page 34: ...s are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you wi...

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