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1
2
1
2
1
0
3
1
1
9
4
5
7
6
8
SW1
4DPT
VDD
1
1
8
8
2
2
7
7
3
3
6
6
4
4
5
5
J9
4X2
J10
4X2
REF SEL
R34
10k
LMH1982
1
1
8
8
2
2
7
7
3
3
6
6
4
4
5
5
TOF OUT
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
TP11
SCL
TP12
SDA
16 PIN
J11
10k
R31
R42
50
I2C_EN
ABL
E
1
3
10k
R32
R43
50
G
EN
L
OC
K
1
4
10k
R33
R44
50
R
ESET
1
5
R45
50
N
O_R
EF
1
6
SC
L
1
2
SD
A
1
1
G
N
D
1
0
9
GREEN
D1
R46
330
50
R36
17
NO_LOCK
D3
18
GND
19
HD_CLK
20
HD_CLK
21
VDD
22
GND
C25
100 nF
C53
10 µF
VDD
R38
NP
(100
Ö
)
100
:
DIFF. IMPEDANCE
0
Ö
(10 nF)
C35
J5
SMA
HD_CLK
0
Ö
(10 nF)
C37
J6
SMA
HD_CLK
23
SD_CLK
24
SD_CLK
R37
NP
(100
:
)
100
:
DIFF. IMPEDANCE
0
Ö
(10 nF)
C31
J3
SMA
SD_CLK
0
Ö
(10 nF)
C34
J4
SMA
SD_CLK
330
R49
GREEN
50
R40
50
R39
4.7k
R16
4.7k
R17
C20
100 nF
VDD
C44
100 nF
VD
D
3
2
L
PF
I
3
1
G
N
D
3
0
VC
XO
2
9
2
8
2
7
G
N
D
2
6
T
O
F
_OU
T
2
5
C26
10 nF
C50
100 nF
C51
100 nF
0
R22
TP1
V
DD
8
VREF_B
7
HREF_B
6
REF_SEL
5
VREF_A
4
HREF_A
3
2
GND
1
VC_FREERUN
50
R41
REF_SEL
50
R6
HREF_B
50
R7
VREF_B
TP30
HREF_B
TP31
VREF_B
50
R25
VREF_A
TP28
VREF_A
50
R14
HREF_A
TP27
HREF_A
C24
100 nF
R13
NP
0
R12
50
R9
50
R10
TP23
TOF_OUT
TOF_OUT
100 nF
C23
C22
100 nF
U5
U8
LMP7701
+
-
C22
100 nF
3
4
1
2
5
C29
100 nF
P1
50k
NP
R27
JP5
U6
LMP7701
+
-
C12
100 nF
3
4
1
2
5
50
:
CONTROLLED
IMPEDANCE TRACE
R8
20k
C28
1 µF
C27
22 µF
C10
22 µF
TP22
VDD_VCXO
TP21
VC_IN
C15
NP
R19
0
1
VC
JP8
OUT
4
GND
X1
CTS357
3
VCXO
DISABLE
EN
2
6
VDD_VCXO
VDD_VCXO
0
R11
TP4
VDD_VCXO
C12
100 nF
C17
1 µF
C43
10 µF
+
C6
47 µF
2
Ö
R5
C14
100 nF
+
C40
NP
VDD
VDD2V5
D
VD
D
VDD
DVDD
VDD
VDD
V
D
D
V
D
D
VDD_VCXO
VCC3V3
VC
C
VDD
VDD
Evaluation Board Schematic
Figure 6. Schematic (4 of 4)
LMH1982 Clock Generator with Loop Filter, VCXO, and LMP7701 Op Amps
10
AN-1841 LMH1982 Evaluation Board
SNOA527A – May 2008 – Revised April 2013
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