Register Tables
5.2
Receiver Registers
Table 6. Receiver Registers
FIELD REGISTER
REGISTER NAME
BITS
DEFAULT
R/RW
DESCRIPTION
ADDRESS
EQ_Boost
Reg 0x03 Channel
4 Stage EQ Boost Levels. Read-back
value going to CTLE in reg_0x52. Used
0x80
for setting EQ value when reg_0x2D[3]
is high
7
eq_BST0[1]
1
RW
2 Bits control for stage 0 of the CTLE.
Adapts during CTLE adaptation
6
eq_BST0[0]
0
RW
5
eq_BST1[1]
0
RW
2 Bits control for stage 1 of the CTLE.
Adapts during CTLE adaptation
4
eq_BST1[0]
0
RW
3
eq_BST2[1]
0
RW
2 Bits control for stage 2 of the CTLE.
Adapts during CTLE adaptation
2
eq_BST2[0]
0
RW
1
eq_BST3[1]
0
RW
2 Bits control for stage 3 of the CTLE.
Adapts during CTLE adaptation
0
eq_BST3[0]
0
RW
SD_EQ
Reg_0x0D Channel
0x00
270 Mbps EQ Boost Setting
7
Reserved
0
RW
6
Reserved
0
RW
5
Reserved
0
RW
4
Reserved
0
RW
3
Reserved
0
RW
2
Reserved
0
RW
1
Reserved
0
RW
Mr_auto_eq_en_bypass
1: EQ Bypass for 270 Mbps
0: Use EQ Settings in reg0x03[7:0] for
270 Mbps
0
0
RW
Note: If 0x13[1] mr_eq_en_bypass is
set, bypass would be set and auto-
bypass has no significance.
EQ_SD_CONFIG
Reg 0x13 Channel
0x90
Channel EQ Bypass and Power Down
7
Reserved
1
RW
sd_0_PD
1: Power Down IN0 Signal Detect
6
0
RW
0: IN0 Signal Detect normal operation
sd_1_PD
1: Power Down IN1 Signal Detect
5
0
RW
0: IN1 Signal Detect normal operation
4
Reserved
1
RW
eq_PD_EQ
Controls the power-state of the selected
channel. The un-selected channel is
always powered-down
3
0
RW
1: Powers down selected channel EQ
stage
0: Powers up EQ of the selected
channel
2
Reserved
0
RW
eq_en_bypass
1: Bypass stage 3 and 4 of CTLE
1
0
RW
0: Enable Stage 3 and 4 of CTLE
0
Reserved
0
RW
23
SNLU183 – September 2015
LMH0318 Programming Guide
Copyright © 2015, Texas Instruments Incorporated
