FRAM EEPROM
Host Processor
MSP430FR5994
TIDM-FRAM-EEPROM
V
CC
Measure
and Sensing
WP
SCL
SDA
VCC
FRAM EEPROM
Host Processor
MSP430FR5994
TIDM-FRAM-EEPROM
VCC Measure/
Sensing
CS
WP
SCLK
MOSI
MISO
Resources
25
SLAU678A – March 2016 – Revised April 2016
Copyright © 2016, Texas Instruments Incorporated
MSP430FR5994 LaunchPad™ Development Kit (MSP
‑
EXP430FR5994)
3.5.2
Operation
The EEPROM emulation is configured to use I
2
C or SPI protocol in Slave mode as indicated by
and
. It would typically be connected to a host processor which would act as the master. This
implementation, unlike traditional EEPROM, requires no caching after several hundred bytes. The host
could continuously write data to memory once the communication is initiated. And the data is immediately
written to memory. This means that the application could continuously stream data with much higher
throughput. The SPI operation also includes DMA.
Figure 18. EEPROM SPI Interface Block Diagram
Figure 19. EEPROM I
2
C Interface Block Diagram
This TI Design also emulates industry standard EEPROM protocols such as I
2
C and SPI, as well as a
write protection pin to ensure that the device is protected from any writes. On top of EEPROM emulation,
the TI Design periodically samples the ADC for the latest VCC and temperature and stores it in FRAM at a
low priority. When the host application requests the data, it is immediately available. The sensor data is
currently configured to periodically sample every second and can be custom tailored for the application.
The sensor reading does not block the EEPROM emulation. The EEPROM emulation is the highest
priority function. For more information on this example please visit the TI Design page at
http://www.ti.com/tool/tidm-eeprom-emulation
4
Resources
4.1
Integrated Development Environments
Although the source files can be viewed with any text editor, more can be done with the projects if they're
opened with a
like Code Composer Studio IDE (CCS) and IAR Embedded
Workbench IDE.
