R2
SHTDN
DUT_GND
JMP8
Pull-up resistor
R1
CLKSEL
DUT_GND
JMP7
Pull-up resistor
R1
CLKSEL
DUT_GND
JMP7
Pull-up resistor
LVDS83BTSSOPEVM Configuration
4
SNLU233 – October 2017
Copyright © 2017, Texas Instruments Incorporated
LVDS83BTSSOPEVM User’s Guide
Figure 2. Clock Rising Edge (High) Jumper Setting
Figure 3. Clock Falling Edge (Low) Jumper Setting
Figure 4. Active Shutdown/Clear Jumper Setting
2.3
Power-Up Sequence
The SN75LVDS83B does not require a specific power-up sequence; however, it is permitted to power up
the IOVCC while VCC, VCCPLL, and VCCLVDS remain powered down and connected to GND. The input
level of Shutdown/Clear during this time does not matter because only the input stage is powered up while
all other devices blocks are still powered down.
Additionally, it is also permitted to power up all 3.3 V power domains while IOVCC is still powered down to
GND. The device will not suffer damage. However, in this case, all the I/Os are detected as logic HIGH,
regardless of the input voltage level. Therefore connecting Shutdown/Clear to GND will still be interpreted
as logic HIGH, consequently turning the LVDS output stage on. The power consumption at this stage is
significantly higher that in standby mode, but lower than normal mode.
The user experience may be impacted by the way a system powers up and powers down an LCD screen.
The following sequences are suggested:
Power-up sequence (SN75LVDS83B SHTDN input initially LOW):
1. Ramp up the LCD power (0.5 ms to 10 ms) with the backlight turned off.
2. Wait an additional 0 to 200 ms to avoid display noise.
3. Enable the video source output – start sending black video data.
