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Texas Instruments Errata MSP430F6736A, Manual

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7 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from April 24, 2019 to May 11, 2021

Page

• Changed the document format and structure; updated the numbering format for tables, figures, and cross 

references throughout the document..................................................................................................................

6

Revision History

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24

MSP430F6736A Microcontroller

SLAZ646S – FEBRUARY 2015 – REVISED MAY 2021

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Copyright © 2021 Texas Instruments Incorporated

Summary of Contents for Errata MSP430F6736A

Page 1: ...visories 3 4 Fixed by Compiler Advisories 3 5 Nomenclature Package Symbolization and Revision Identification 4 5 1 Device Nomenclature 4 5 2 Package Markings 4 5 3 Memory Mapped Hardware Revision TLV...

Page 2: ...M11 PMM12 PMM14 PMM15 PMM18 PMM20 PMM26 PORT15 PORT19 SD3 UCS11 USCI36 USCI37 USCI41 USCI42 USCI47 USCI50 2 Preprogrammed Software Advisories Advisories that affect factory programmed software The che...

Page 3: ...umber Rev B CPU21 CPU22 CPU40 Refer to the following MSP430 compiler documentation for more details about the CPU bugs workarounds TI MSP430 Compiler Tools Code Composer Studio IDE MSP430 Optimizing C...

Page 4: ...ting null Fully qualified development support product XMS devices and X development support tools are shipped against the following disclaimer Developmental product is intended for internal evaluation...

Page 5: ...guidance on how to locate the TLV structure and read out the HW_ID can be found in the device User s Guide www ti com Nomenclature Package Symbolization and Revision Identification SLAZ646S FEBRUARY 2...

Page 6: ...l repeat sequence of channels ADC12CTL1 ADC12CONSEQx In addition the timer overflow flag cannot be used to detect an overflow ADC12IFGR2 ADC12TOVIFG Workaround 1 For manual trigger mode ADC12CTL0 ADC1...

Page 7: ...vel lower levels increase probability defining the switching level in software controlled mode applicable to DVCC only Scenario 2 When a battery is connected to DVCC AUXVCC1 or AUXVCC2 as the first vo...

Page 8: ...SL_REQ_JTAG_OPEN in the return value has been disabled in this device Workaround None CPU21 CPU Module Category Compiler Fixed Function Using POPM instruction on Status register may result in device h...

Page 9: ...ates an INFOD Flash memory erase the program counter is corrupted Workaround None NOTE This erratum applies to debug mode only CPU40 CPU Module Category Compiler Fixed Function PC is corrupted when ex...

Page 10: ...st Stack Pointer increment is followed by an unintended read access to the memory If this read access is performed on vacant memory the VMAIFG will be set and can trigger the corresponding interrupt S...

Page 11: ...on e g ret push call pop jmp br is fetched from the last addresses last 4 or 8 byte of a memory e g FLASH RAM FRAM that is not contiguous to a higher valid section on the memory map In debug mode usin...

Page 12: ...nfigured to transfer bytes from the eUSCI_A or eUSCI_B transmit or receive buffers the transmit or receive triggers TXIFG and RXIFG may not be seen by the DMA module and the transfer of the bytes is m...

Page 13: ...d the line that clears the DMAEN bit the DMA always requests the bus and the JTAG system never gains control of the device Workaround When operating the DMA in repeat burst block transfer mode set bre...

Page 14: ...eliable debug session or general issues with JTAG device connectivity and the resulting bad customer experience Texas Instruments has chosen to remove the LPMx 5 debug support feature from common MSP4...

Page 15: ...n Programmer use v1 2 3 0 or later 3 For custom programming solutions refer to the specification on MSP430 Programming Via the JTAG Interface User s Guide SLAU320 revision V or newer and use MSPDebugS...

Page 16: ...rmance mode and mask CPU execution for 150 us on wakeup from LPM3 and LPM4 However when the low side SVS and the SVM are disabled or are operating in full performance mode SVMLE 0 and SVSLE 0 or SVMLF...

Page 17: ...ode SVSMLCTL SVSLFP 0 This provides a settling time delay of approximately 150us allowing the core sufficient time to increase to the expected voltage before the delay expires PMM15 PMM Module Categor...

Page 18: ...e wakeup time from LPM2 3 4 to twakeupslow 150 us or Do not configure the SVSH SVMH such that the modules transition from Normal mode to an OFF state on LPM entry and ensure SVSH SVMH is in manual mod...

Page 19: ...In this mode a POR should typically be triggered when DVCC reaches 3 75V If the OVP feature of SVM high side is enabled going into LPM234 the SVM might trigger at DVCC voltages below 3 6V 3 5V within...

Page 20: ...o SVSMLCTL and only if the code that checks for SVSMLDLYIFG 1 is implemented without a timeout The device will be stuck in the polling loop polling since SVSMLDLYIFG will never be cleared Workaround F...

Page 21: ...CSCTL4 register will correctly configure the respective clock to use the intended clock source but might also erroneously set XT1 XT2 fault flag if the crystals are not present at XT1 XT2 or not confi...

Page 22: ...stuck to 1 or start toggling after transmission is completed This happens in all four combinations of Clock Phase and Clock Polarity options UCAxCTLW0 UCCKPH UCAxCTLW0 UCCKPL bits as well as in Master...

Page 23: ...to detect communication failure condition where UCRXIFG is not set check both UCRXIFG and UCTXIFG If UCTXIFG is set twice but UCRXIFG is not set reset the MSP SPI slave by setting and then clearing th...

Page 24: ...2019 to May 11 2021 Page Changed the document format and structure updated the numbering format for tables figures and cross references throughout the document 6 Revision History www ti com 24 MSP430...

Page 25: ...are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and...

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