Demo Board Connections
9
SNLU241A – December 2018 – Revised April 2019
Copyright © 2018–2019, Texas Instruments Incorporated
DS90Ux941AS-Q1EVM User's Guide
(1)
Only set one high
Table 12. Configuration Select (MODE_SEL1) - SW-DIP8 - S6
(1)
MODE
NO.
V
TARGET
VOLTAGE RANGE
V
TARGET
STRAP
VOLTAGE
SUGGESTED STRAP
RESISTORS (1% TOL)
CLOCK
COAX
DISABLE
DSI
V
MIN
V
TYP
V
MAX
(V); V
(VDD18)
= 1.8 V
R
5
(k
Ω
)
R
6
(k
Ω
)
0
0
0
0.126 ×
V
(VDD18)
0
OPEN
10.0
0
0
0
1
0.179 ×
V
(VDD18)
0.211 ×
V
(VDD18)
0.244 ×
V
(VDD18)
0.380
73.2
20.0
0
0
1
2
0.272 ×
V
(VDD18)
0.325 ×
V
(VDD18)
0.364 ×
V
(VDD18)
0.585
60.4
30.1
0
1
0
3
0.404 ×
V
(VDD18)
0.441 ×
V
(VDD18)
0.472 ×
V
(VDD18)
0.794
51.1
40.2
0
1
1
4
0.526 ×
V
(VDD18)
0.556 ×
V
(VDD18)
0.590 ×
V
(VDD18)
1.001
40.2
51.1
1
0
0
5
0.643 ×
V
(VDD18)
0.673 ×
V
(VDD18)
0.708 ×
V
(VDD18)
1.211
30.1
61.9
1
0
1
6
0.763 ×
V
(VDD18)
0.790 ×
V
(VDD18)
0.825 ×
V
(VDD18)
1.421
18.7
71.5
1
1
0
7
0.880 ×
V
(VDD18)
V
(VDD18)
V
(VDD18)
1.8
10
OPEN
1
1
1
The strapped values can be viewed and/or modified in the following register locations:
•
SPLIT : Latched into DUAL_CTL(0x5B[2:0]).
•
DSI LANES : Latched into BRIDGE_CTL (0x4F[3:2]).
•
CLOCK : Latched into BRIDGE_CTL (0x4F[7]).
•
COAX : Latched into DUAL_CTL(0x5B[7]).
•
DISABLE DSI : Latched into RESET (0x01[3]).
(1)
Only set one high.
Table 13. IDx SW-DIP8 - S3
(1)
DESIGNATOR
7-BIT ADDRESS
8-BIT ADDRESS
S3.1
(Default)
0x0C
0x18
S3.2
0x0E
0x1C
S3.3
0x10
0x20
S3.4
0x12
0x24
S3.5
0x14
0x28
S3.6
0x16
0x2C
S3.7
0x18
0x30
S3.8
0x1A
0x34
