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D
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5/11/2016
DS90UB964Q__HUB.SchDoc
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DS90UB964Q1_EVM
Project Title:
Designed for:
Public Release
Assembly Variant:
[No Variations]
©
Texas Instruments
2015
Drawn By:
Engineer:
Dac Tran
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
Version control disabled
SVN Rev:
SV601176
Number:
Rev:
A
GND
RIN0_P
RIN0_N
RIN1_P
RIN1_N
RIN2_P
RIN2_N
RIN3_P
RIN3_N
REFCLK
VDD18_P
VDD18_P
VDD18_P
VDD18_P
VDD18A
VDDIO
CMLOUT_P
CMLOUT_N
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
CSI0_D0_P
CSI0_D0_N
CSI0_D1_P
CSI0_D1_N
CSI0_D2_P
CSI0_D2_N
CSI0_D3_P
CSI0_D3_N
CSI1_D0_P
CSI1_D0_N
CSI1_D1_P
CSI1_D1_N
CSI1_D2_P
CSI1_D2_N
CSI1_D3_N
CSI1_D3_P
CSI0_CLK_P
CSI0_CLK_N
CSI1_CLK_P
CSI1_CLK_N
I2C_SCL
I2C_SDA
I2C_SCL2
I2C_SDA2
IDX
PDB
MODE
INTB
I2C_SCL
I2C_SDA
IDX
PDB
I2C_SCL2
I2C_SDA2
MODE
INTB
REFCLK
CSI0_D3_N
CSI1_D2_N
CSI0_D3_P
CSI0_D0_P
CSI0_D0_N
CSI0_D1_P
CSI0_D1_N
CSI0_D2_N
CSI0_D2_P
CSI1_D0_P
CSI1_D3_P
CSI1_D0_N
CSI1_D1_P
CSI1_D1_N
CSI1_D2_P
CSI1_D3_N
CSI0_CLK_P
CSI0_CLK_N
CSI1_CLK_P
CSI1_CLK_N
RIN0_P
RIN0_N
RIN1_P
RIN1_N
RIN2_P
RIN2_N
RIN3_P
RIN3_N
VDDL_1V1
VDDCSI_1V1
VDDFPD_1V1
VDDFPD18
OPEN: I2C Address = 0x30 (7'b)
GND
IDX
GND
40.2k
R29
0.1
µ
F
C63
TESTEN
GND
0.1
µ
F
C59
0.01
µ
F
C60
GND
VDDIO
REFCLK
MODE
GND
VDD1V8
13.3k
R10
210k
R15
56.2k
R9
68.1k
R8
137k
R14
82.5k
R7
102k
R13
GND
0.1
µ
F
C64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
J2
TSW-108-07-G-D
GND
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
6
3
1
8
2
7
5
4
S1
219-4LPST
1
4
SW1A
219-2LPST
2
3
SW1B
219-2LPST
GND
10k
R16
10k
R17
TESTEN
PDB
GND
10k
R5
0
R1
0
R3
0
R11
4
1
2
3
J4
0022112042
GND
4.7pF
C68
4.7pF
C67
0
R25
0
R27
I2C_SDA
I2C_SCL
0.1
µ
F
C61
GND
4.7k
R21
4.7k
R20
I2C_SCL
I2C_SDA
VDD_I2C
4
1
2
3
J5
0022112042
GND
4.7pF
C70
4.7pF
C69
0
R26
0
R28
I2C_SDA2
I2C_SCL2
0.1
µ
F
C62
GND
4.7k
R23
4.7k
R22
I2C_SCL2
I2C_SDA2
VDD_I2C
R
E
S
E
R
V
E
D
R
A
W
12
L
F
(
91
3)
R
A
W
12
H
F
(
91
3)
R
A
W
10
(
91
3)
S2
KSR221GLFS
10
µ
F
C65
VDDIO
GND
10
µ
F
C1
VDD18A
VDD1V8
120 ohm
L1
1
µ
F
C3
0.1
µ
F
C4
0.01
µ
F
C5
GND
10
µ
F
C12
120 ohm
L3
VDDFPD18
0.01
µ
F
C16
0.01
µ
F
C17
0.01
µ
F
C18
0.01
µ
F
C19
1
µ
F
C14
0.1
µ
F
C15
GND
120 ohm
L5
VDD18_P
1
µ
F
C28
0.1
µ
F
C29
0.01
µ
F
C30
GND
10
µ
F
C42
VDDIO
VDD1V8
VDD33
1
2
3
J1
TSW-103-07-G-S
120 ohm
L6
GND
10
µ
F
C31
VDD1V1
VDDFPD_1V1
120 ohm
L4
GND
10
µ
F
C20
VDDCSI_1V1
120 ohm
L2
10
µ
F
C6
VDDL_1V1
GND
120 ohm
L8
0.01
µ
F
C10
0.01
µ
F
C11
1
µ
F
C8
0.1
µ
F
C9
0.01
µ
F
C24
0.01
µ
F
C25
1
µ
F
C22
0.1
µ
F
C23
0.01
µ
F
C35
0.01
µ
F
C36
1
µ
F
C33
0.1
µ
F
C34
1
µ
F
C44
0.1
µ
F
C45
0.01
µ
F
C46
REFCLK
MODE
IDX
10
µ
F
C26
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
1
2
J3
GND
0
R12
100
R2
GND
10.0k
R30
10.0k
R24
0
R18
TESTEN
REFCLK
0
R31
i
LABEL "REF_CLK
INTB
470
R4
GND
100k
R6
VDD33
Green
2
1
D1
TP2
DNL
1
2
J34
SHORTED: I2C Address = 0x3d (7'b)
VDD1V8
VDD1V8
VDDIO
0.01
µ
F
C41
0.01
µ
F
C52
0.01
µ
F
C58
1
2
3
Q1
BSS138
TP1
i
LABEL "CMLOUTP"
i
LABEL "CMLOUTN"
4.7k
R76
VDDIO
27pF
C66
27pF
C71
VDD18_P3
1
VDD18_P2
2
PDB
3
TESTEN
4
REFCLOCK
5
INTB
6
I2C_SDA2
7
I2C_SCL2
8
GPIO[0]
9
GPIO[1]
10
I2C_SDA
11
I2C_SCL
12
VDDL1
13
GPIO[2]
14
GPIO[3]
15
VDDIO
16
GPIO[4]
17
GPIO[5]
18
GPIO[6]
19
GPIO[7]
20
VDD_CSI0
21
CSI0_CLK-
22
C
23
CSI0_D0-
24
25
CSI0_D1-
26
27
CSI0_D2-
28
29
CSI0_D3-
30
31
VDD18A
32
VDD_CSI1
33
CSI1_CLK-
34
C
35
CSI1_D0-
36
37
CSI1_D1-
38
39
CSI1_D2-
40
41
CSI1_D3-
42
43
VDDL2
44
MODE
45
IDX
46
VDD18_P1
47
VDD18_P0
48
VDD18_FPD0
49
RIN0+
50
RIN0-
51
VDD_FPD1
52
RIN1+
53
RIN1-
54
VDD18_FPD1
55
LPTXP
56
LPTXN
57
VDD18_FPD2
58
RIN2+
59
RIN2-
60
VDD_FPD2
61
RIN3+
62
RIN3-
63
VDD18_FPD3
64
DAP
65
U1
DS90UB964TRGCRQ1
VDD_I2C
0.1
µ
F
C47
0.1
µ
F
C53
E/D
1
GND
2
OUTPUT
3
VCC
4
25 MHz
Y1
KC5032A25.0000CMGE00
1
2
25 MHz
Y2
Assembly Note
ZZ6
Place Jumper on J34
SH-J2
Assembly Note
ZZ5
Place Jumper on J1.1-2
SH-J1
0
R19
0
R146
10
µ
F
C2
10
µ
F
C13
10
µ
F
C27
10
µ
F
C7
10
µ
F
C21
10
µ
F
C32
10
µ
F
C43
100 ohm diff pair. +/-5%.
Resistors have to be placed
close to U1.
+/- 10 mil for all inter/intra
pairs.
Layout note: For all differential pairs(CSI-2 and FPD) in this
design follow the guidelines decribed below: Route together
with controlled differential 100ohm impedance and controlled
single ended 50ohm impedance. Keep away from other high
speed signals. Keep lengths within 10mil of each other. Keep
traces on layers adjacent to the ground plane. Keep the
number of VIAS to minimum. If VIAS are used, make it
symetrical through all signals. Keep diff pairs separated at
least by x3 of the trace width. NO STUBS on the signal path,
components should be placed such that the signals can routed
in pass-through manner.
Place 10uF, 1uF, 0.1uF
and 0.01uF bypass caps on
bottom of board, close to
U1 VDD pins
47
SNLU177 – July 2016
Copyright © 2016, Texas Instruments Incorporated
PCB Schematics