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ALP Software Setup
24
SNLU177 – July 2016
Copyright © 2016, Texas Instruments Incorporated
DS90UB96X-Q1EVM User's Guide
time.sleep(0.1)
"CSI_EN"
board.WriteReg(0x33,0x1) # CSI_EN & CSI0 4L
time.sleep(0.1)
"FWD_PORT"
board.WriteReg(0x20,0xd0) # forwarding of RX 1 to CSI0
time.sleep(0.1)
"FPD3_PORT_SEL"
board.WriteReg(0x4c,0x12) # RX_PORT1
time.sleep(0.1)
"enable pass throu"
board.WriteReg(0x58,0x58) # enable pass throu
time.sleep(0.1)
board.WriteReg(0x5c,0x1a) #
"SER_ALIAS_ID 0x5c value ", hex(board.ReadReg(0x5c))
time.sleep(0.1)
board.WriteReg(0x5d,0x60) #
"SlaveID[0] 0x5d value ", hex(board.ReadReg(0x5d))
time.sleep(0.1)
board.WriteReg(0x65,0x62) #
"SlaveAlias[0] 0x65 value ", hex(board.ReadReg(0x65))
time.sleep(0.1)
"FV_POLARITY"
board.WriteReg(0x7c,0x01) # FV active low
time.sleep(0.1)
"YUV422 DT"
board.WriteReg(0x70,0x5f) # VC1 and CSI0 datatype 0x1f yuv422_10b
time.sleep(0.1)
"FPD_MODE"
board.WriteReg(0x6d,0x7f) # 913A 10-bit mode
time.sleep(0.1)
#########################################################
# 964_RX2_init_CSI0.py
"CSI_PORT_SEL"
board.WriteReg(0x32,0x01) # CSI0 select
time.sleep(0.1)
"CSI_PLL_CTL"
board.WriteReg(0x1f,0x02) # CSI0 800mbps
time.sleep(0.1)
"CSI_EN"
board.WriteReg(0x33,0x1) # CSI_EN & CSI0 4L
time.sleep(0.1)
"FWD_PORT"
board.WriteReg(0x20,0xb0) # forwarding of RX 2 to CSI0
time.sleep(0.1)
"FPD3_PORT_SEL"
board.WriteReg(0x4c,0x24) # RX_PORT2
time.sleep(0.1)
"enable pass throu"