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2 Description

2.1 Redriver-Mux 5-Level I/O Control Inputs

Each DS320PR412, DS320PR421, SN75LVPE5412 and SN75LVPE5421 features 5-level input pins (MODE, 
GAIN/SDA, EQ0/ADDR, EQ1, and RX_DET/SCL) that are used to control the configuration of the device. These 
5-level inputs use a resistor divider to help set the five valid levels to provide a wider range of control settings.

Table 2-1. Five-Level Control Pin Settings

PIN LEVEL

PIN SETTING

L0

1 kΩ to GND

L1

8.25K Ω to GND

L2

24.9 Ω to GND

L3

75 Ω to GND

L4

Float

2.2 Redriver-Mux Modes of Operation

Each DS320PR412, DS320PR421, SN75LVPE5412 and SN75LVPE5421 can be configured to operate in either 
Pin Mode, SMBus Mode, or I2C Slave Mode. The mode of operation of the redriver is determined by the pin 
strap setting on the MODE pin as shown in 

Table 2-2

.

Table 2-2. Modes of Operation

MODE PIN LEVEL

MODE OF OPERATION

L0

Pin Mode

L1

SMBus Mode or I2C Slave Mode

L2

SMBus Mode or I2C Slave Mode

L3

RESERVED

L4

RESERVED

2.3 Redriver-Mux SMBus or I2C Register Control Interface

The DS320PR412, DS320PR421, SN75LVPE5412 and SN75LVPE5421 internal registers can be accessed 
through standard SMBus protocol. The DS320PR412, DS320PR421, SN75LVPE5412 and SN75LVPE5421 
features two banks of channels, Bank 0 (Channels 0-1) and Bank 1 (Channels 2-3), each featuring a separate 
register set and requiring a unique SMBus slave address. The SMBus slave address pairs (one for each channel 
bank) are determined at power up based on the configuration of the MODE and EQ0/ADDR pins. The pin state 
is read on power up, after the internal power-on reset signal is deasserted.

There are 8 unique SMBus slave address pairs (one address for each channel bank) that can be assigned to 
the device by placing external resistor straps on the MODE and EQ0/ADDR pins as shown in 

Table 2-3

. When 

multiple DS320PR412, DS320PR421, SN75LVPE5412 and SN75LVPE5421 devices are on the same SMBus 
interface bus, each channel bank of each device must be configured with a unique SMBus slave address pair.

Table 2-3. Redriver-Mux SMBus Address Map

MODE

EQ0/ADDR Pin Level

Channels 0-1:

7-Bit Address [HEX]

Channels 2-3:

7-Bit Address [HEX]

L1

L0

0x18

0x19

L1

L1

0x1A

0x1B

L1

L2

0x1C

0x1D

L1

L3

0x1E

0x1F

L2

L0

0x20

0x21

L2

L1

0x22

0x23

L2

L2

0x24

0x25

L2

L3

0x26

0x27

Description

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4

DS320PR412-421EVM User's Guide

SNLU301 – NOVEMBER 2021

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Copyright © 2021 Texas Instruments Incorporated

Summary of Contents for DS320PR412-421EVM

Page 1: ...20PR421 are interchangeable with SN75LVPE5421 Figure 1 1 DS320PR412 421EVM Table of Contents 1 Introduction 3 1 1 Features 3 1 2 Applications 3 2 Description 4 2 1 Redriver Mux 5 Level I O Control Inp...

Page 2: ...ure 4 5 Layer 5 22 Figure 4 6 Bottom Layer 22 List of Tables Table 2 1 Five Level Control Pin Settings 4 Table 2 2 Modes of Operation 4 Table 2 3 Redriver Mux SMBus Address Map 4 Table 2 4 Equalizatio...

Page 3: ...annel unidirectional linear redrivers operating at rates up to 32Gbps DS320PR412 linear redriver with 1 2 MUX DS320PR421 linear redriver with 2 1 DEMUX Linear equalization for seamless support of link...

Page 4: ...ssed through standard SMBus protocol The DS320PR412 DS320PR421 SN75LVPE5412 and SN75LVPE5421 features two banks of channels Bank 0 Channels 0 1 and Bank 1 Channels 2 3 each featuring a separate regist...

Page 5: ...14 L2 L4 15 L3 L0 16 L3 L1 17 L3 L2 18 L3 L3 19 L3 L4 The equalization gain of each channel of each device can also be set by writing to SMBus I2C registers in I2C Mode 2 5 Redriver Mux RX Detect Sta...

Page 6: ...rol When operating in Pin Mode the GAIN SDA pin can be used to set the overall datapath DC low frequency gain of the DS320PR412 DS320PR421 SN75LVPE5412 and SN75LVPE5421 as shown in Table 2 6 Please re...

Page 7: ...A B 5 6 Edge Finger to PCIe A J7 PCIe TDI 1 2 Edge Finger to PCIe B 3 4 Edge Finger to PCIe A B 5 6 Edge Finger to PCIe A J8 PCIe TDO 1 2 Edge Finger to PCIe B 3 4 Edge Finger to PCIe A B 5 6 Edge Fi...

Page 8: ...J30 DS320PR412_0 RX_DET_SCL_0 1 2 L0 3 4 L1 5 6 L2 7 8 L3 N C L4 9 10 SCL J23 DS320PR412_0 GAIN_SDA 1 2 L0 3 4 L1 5 6 L2 7 8 L3 N C L4 9 10 SDA JMP4 DS320PR412_1 EQ0_ADDR_0 1 2 L0 3 4 L1 5 6 L27 8 L3...

Page 9: ...DS320PR421_0 RX_DET_SCL_0 1 2 L0 3 4 L1 5 6 L27 8 L3 N C L4 9 10 SCL J27 DS320PR421_0 GAIN_SDA 1 2 L0 3 4 L1 5 6 L27 8 L3 N C L4 9 10 SDA JMP14 DS320PR421_1 EQ0_ADDR_0 1 2 L0 3 4 L1 5 6 L27 8 L3 N C...

Page 10: ...drivers is enabled by leaving RX_DET pin open 2 The redrivers are enabled PWDN pins tied to GND 3 The board is configured for any PCIe bus width 4 DC Gain of all redrivers is set to 0 dB by leaving th...

Page 11: ...dvark Adapter to P4 Note that the Adapter is not supplied with the DS320PR412 421EVM Install shunt on JMP17 across pins 1 2 for USB2ANY 3 4 for Aardvark 2 Install SigCon Architect Version 3 0 0 16 app...

Page 12: ...to apply the selected settings and click the Apply to All Channels button Figure 2 1 SigCon Architect DS320PR412 421 High Level Page Description www ti com 12 DS320PR412 421EVM User s Guide SNLU301 N...

Page 13: ...3 1 through Figure 3 9 show the EVM schematics Figure 3 1 DS320PR412 www ti com Schematics SNLU301 NOVEMBER 2021 Submit Document Feedback DS320PR412 421EVM User s Guide 13 Copyright 2021 Texas Instru...

Page 14: ...Figure 3 2 DS320PR421 Schematics www ti com 14 DS320PR412 421EVM User s Guide SNLU301 NOVEMBER 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated...

Page 15: ...3 3 Configuration Headers Figure 3 4 I2C Adapter Selection www ti com Schematics SNLU301 NOVEMBER 2021 Submit Document Feedback DS320PR412 421EVM User s Guide 15 Copyright 2021 Texas Instruments Incor...

Page 16: ...Figure 3 5 Power Schematics www ti com 16 DS320PR412 421EVM User s Guide SNLU301 NOVEMBER 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated...

Page 17: ...Figure 3 6 EDGE Finger www ti com Schematics SNLU301 NOVEMBER 2021 Submit Document Feedback DS320PR412 421EVM User s Guide 17 Copyright 2021 Texas Instruments Incorporated...

Page 18: ...igure 3 7 PCIe Clock Figure 3 8 PCIe x8 Connector A Schematics www ti com 18 DS320PR412 421EVM User s Guide SNLU301 NOVEMBER 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated...

Page 19: ...Figure 3 9 PCIe x16 Connector B www ti com Schematics SNLU301 NOVEMBER 2021 Submit Document Feedback DS320PR412 421EVM User s Guide 19 Copyright 2021 Texas Instruments Incorporated...

Page 20: ...gure 4 6 illustrate the EVM PCB layout images Figure 4 1 Top Layer Figure 4 2 Layer 2 PCB Layouts www ti com 20 DS320PR412 421EVM User s Guide SNLU301 NOVEMBER 2021 Submit Document Feedback Copyright...

Page 21: ...Figure 4 3 Layer 3 Figure 4 4 Layer 4 www ti com PCB Layouts SNLU301 NOVEMBER 2021 Submit Document Feedback DS320PR412 421EVM User s Guide 21 Copyright 2021 Texas Instruments Incorporated...

Page 22: ...Figure 4 5 Layer 5 Figure 4 6 Bottom Layer PCB Layouts www ti com 22 DS320PR412 421EVM User s Guide SNLU301 NOVEMBER 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated...

Page 23: ...R60J474KE19D 10 2 C80 C82 22uF Murata GRM188C80G226MEA0D 11 11 C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 C93 1pF Murata Electronics GRM1555C1H1R0CA01D 12 2 D1 D2 LED Green 0805 13 12 JMP1 JMP2 JMP3 JMP4...

Page 24: ...ctronic Components ERJ 2RKF1053X 35 1 R91 205K Panasonic Electronic Components ERJ 2RKF2053X 36 1 R92 5 76K Panasonic Electronic Components ERJ 2RKF5761X 37 3 R93 R131 R132 10K Panasonic Electronic Co...

Page 25: ...nts 46 1 U5 TMUX1133PWR Texas Instruments 47 1 U6 TPS548B22RVFT Texas Instruments TPS548B22RVFT 48 1 U7 SN74LVC125A_PW_1 4 Texas Instruments SN74LVC125AQPWRQ1 49 1 U8 LMK00334RTVR Texas Instruments ww...

Page 26: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Page 27: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Page 28: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Page 29: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Page 30: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Page 31: ...change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of thes...

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