1
1
2
2
3
3
4
4
5
5
6
6
D
D
C
C
B
B
A
A
1
1
5/13/2014
DRV8846EVM_RevA.SchDoc
Sheet Title:
Size:
Mod. Date:
File:
Sheet:
of
B
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DRV8846EVM
Project Title:
Designed for:
Public Release
Assembly Variant:
001
© Tex as Instruments
2014
Drawn By:
Engineer:
Rick Duncan
Te xas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Te xas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Te xas Instruments and/or its
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
Not in version control
SVN Rev:
DRV8846EVM
Number:
Rev:
A
10µF
C1
VM
AOUT2
AOUT1
TOFF_SEL
10
nENBL
11
STEP
12
DIR
13
VREF
14
VM
15
NC
16
VINT
17
GND
18
ADEC
19
I0
20
I1
21
DEC0
22
nSLEEP
23
DEC1
24
P
P
A
D
2
5
AOUT1
1
AISEN
2
AOUT2
3
BOUT2
4
BISEN
5
BOUT1
6
nFAULT
7
MO
8
M1
9
U1
DRV8846RGE
DEC1
GND
AOUT1
DEC0
GND
AOUT2
BOUT1
BISEN
BOUT2
DRV8846
nFAULT notification
GND
nFAULT
C
1
A
2
D1
D_LED_603_RED
0.1µF
C2
2.2µF
C3
1
2
J1
ED555/2DS
nSLEEP
nFAULT
4.99k
R3
BOUT1
BOUT2
VM
AISEN
VINT
VREF
DIR
I1
I0
M0
M1
TOFF_SEL
nENBL
STEP
ADEC
0.25
R1
0.25
R2
GND
510
R4
1
2
J2
ED555/2DS
1
2
J3
ED555/2DS
MSP_M1
MSP_TOFF_SEL
MSP_VREF
MSP_VINT
MSP_I0
MSP_I1
MSP_DEC0
MSP_DEC1
MSP_nFAULT
MSP_nSLEEP
MSP_ADEC
MSP_DIR
MSP_nENBL
MSP_STEP
MSP_M0
nSLEEP
ADEC
DIR
nENBL
STEP
M0
M1
TOFF_SEL
VREF
VINT
I0
I1
DEC0
DEC1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R5
EXB-2HV330JV
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R6
EXB-2HV330JV
DEC1
DEC0
I1
I0
VINT
VREF
TOFF_SEL
M1
DIR
M0
STEP
nENBL
ADEC
nSLEEP
nFAULT
A
O
U
T
1
A
O
U
T
2
TEST POINTS & DEBUG MODE
B
O
U
T
1
B
O
U
T
2
V
M
VM
GND2
AOUT1
AOUT2
BOUT1
BOUT2
GND
GND
nFAULT
Remove R4 to
disable current flow
through diode
Motor Supply and
Outputs
VM range 4 to 16V
Connection to microcontroller
or external interface
Notes:
1) For normal operation, populate resistor packs R5 and R6
2) For external control, remove resistor packs R5,R6 and provide signals at J4
3) Signals can be observed at J4 during normal operation
GND
1
GND
2
GND1
D3082-05
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
J4
HEADER_1X18
V3P3R
V3P3
V3P3R
V3P3R
GND
0.1µF
C12
GND
Introduction
2.7
Schematic and Bill of Materials (BOM)
2.7.1
DRV8846 Schematic
and
illustrate the schematics for this EVM.
Figure 2. DRV8846 Schematic (1 of 2)
9
SLLU203A – June 2014 – Revised March 2015
DRV8846 Evaluation Module
Copyright © 2014–2015, Texas Instruments Incorporated