Texas Instruments DM38x DaVinci, User Manual

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YCbCr to RGB
conversion
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C
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(d
ly
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DTG
(Display Timing
Generator)
CLK1X
HD_VENC
RGB or
YCbCr
B[9:0]
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Gamma
Correction
Gamma
Correction
Gamma
Correction
dtv_fid
dtv_vs
dtv_vbi
dtv_hs
dtv_hbi
dtv_actvid
Config
Registers
actvid_sel
4
4
4
to
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2
2
EmbSync
Out
dvo_d0
dvo_d1
dvo_d2
dvo_hs
dvo_vs
dvo_actvid
dvo_fid
O
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G[9:0]
R[9:0]
B[9:0]
CLK2X
Component
Out
RGB
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Internal Modules
129 SPRUHI7A – December 2012 – Revised June 2016
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Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
Figure 1-72. HD VENC Block Diagram
1.2.7.3 Video Data Interface to OSD
1.2.7.3.1 OSD Interface Overview
The interface between OSD and video display encoder are consisting of a 30-bit data bus, a pixel clock
and five sync signals. By default 30-bit RGB video data will be passed from OSD to encoders on every
rising edge of the pixel clock during active video period. The maximum frequency of the pixel clock is
148.5 MHz.
Table 1-45 lists all the control signals of this interface.
Table 1-45. OSD Interface Signals
Signal Names Descriptions
dtv_fid Field ID signal. This signal will toggle between “1” and “0” on every field in interlace mode. It will
toggle between “1” and “0” on every frame in progressive mode.
Programmability: controlled by register CFG13 (END_F1) and CFG10 (LINES).
dtv_vs Vertical sync signal. This signal is a one-line long pulse. This pulse indicates the first line of each
field in interlace mode. In progressive mode, it indicates the first line of each frame.
Programmability: location of this signal is controlled V_BLANK1, VBLANK2, and FD1.
dtv_vbi Vertical blank interval signal. This signal goes to “1” during non-active video period; it stays at “0”
during active video period.
Programmability: controlled by register CFG16/17. (For OSD interface only)
dtv_hs Horizontal sync signal. This is the horizontal sync signal.
Programmability; the start location and width of this signal are both programmable. They are
controlled by CFG17. (For OSD interface only)
dtv_hbi This is a four-pixels-wide and active-high signal. It appears once every video line.
Programmability: The location of this pulse is programmable. (For OSD interface only)
dtv_actvid This is active-video qualification signal. When this signal is high, encoder is expecting active video
data output from OSD after one clock delay.
Programmability: The fully programmable. (For OSD interface only)
Note: The dtv_vs, dtv_vbi, dtv_hs and dtv_hbi signals are generated by the encoder but are not used by
the HDVPSS design. Therefore, all parameters related to these signals do not need to be specified.