0
Base
H Counter
hdin
1
2
3
4
5
6
7
clk2x
2 clk
White 100%
Black
Blanking
AV_H_STA
AV_H_STP
Blanking Edge
Shaping Disable
Blanking Edge
Shaping Enable
Active Video Sidth =
AV_H_STP - AV_H_STA
Internal Modules
105
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.2.6.2.3.6 Horizontal Blanking Edge Shaping
Horizontal video blanking edge is shaped so that the output video has the proper blanking transition.
This feature is enabled by default but can be disabled by setting 1 to the BLS register.
shows
the waveforms when blanking edge shaping is enabled and disabled.
Figure 1-57. Horizontal Blanking Shaping
1.2.6.2.3.7 Slave Mode Timings
1.2.6.2.3.7.1 Slave Mode Horizontal Timing
shows slave mode horizontal timing. The hdin acts as a horizontal sync input. The internal
base horizontal counter is reset after two clk2x cycles upon detecting a rising edge of hdin. The polarity of
hdin can be inverted by the HIP register.
Figure 1-58. Slave Mode Horizontal Timing
1.2.6.2.3.7.2 Slave Mode Vertical Timings
, and
show the slave mode vertical timing. The vdin acts as a vertical
sync input. The internal base vertical counter is reset when vdin rise transition is detected at hdin rising
edge or 0.5H position for the interlaced mode. If vdin is behind hdin assertion. Vertical reset is suspended
until the next hdin rise edge or the next 0.5H for the interlaced mode.