0
0H
Base H Counter
1
2
3
60
63
64
65
66
67
clk2x
61
63 clk
62
DAC Video Output
0
1
2
3
4
TV H Counter
TV V Counter
Sync 50%
0
0H
Base H Counter
1
2
3
70
71
72
73
74
75
clk2x
76
73 clk
77
DAC Video Output
0
1
2
3
4
TV H Counter
TV V Counter
Sync 50%
Internal Modules
103
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
and
show the DAC video output pipeline delay against the internal base counter.
The pipeline delay latency is determined by the input pixel rate. The input pixel rate is specified by the
PXLR register. The SDTV input pixel rate is typically 13.5 MHz, which is half of clk2x (PXLR = 0).
However, some unusual systems may apply the 27 MHz input pixel rate. It is possible to set PXLR = 1.
Figure 1-53. SDTV DAC Video Output Pipeline Delay (PXLR = 0)
Figure 1-54. SDTV DAC Video Output Pipeline Delay (PXLR = 1)
