Board Layout
4
Board Layout
This demonstration board is a two-layer PCB. It has separate ground and power planes in the inner layers.
The ground plane has been opened up around op amp pins sensitive to capacitive loading. Power-supply
planes are laid out to keep current-loop areas to a minimum. J1, J2 and J4 are to be mounted horizontally
onto the board edge. J3, and J4 are to be mounted vertically onto the board. The location and type of
capacitors used for power-supply bypassing are crucial to high-frequency amplifiers. The tantalum
capacitors, C
3
and C
4
, do not need to be as close to pins 1 and 5 on the PCB and may be shared with
other amplifiers. See the individual amplifier data sheets for more information on proper board layout
techniques and component selection.
5
Measurement Tips
This demonstration board, and the component values shown, is designed to operate in a 75
Ω
environment
for the input and output and 50
Ω
environment for the EN and SEL control pins. Most data sheet plots are
obtained under these conditions. It is easy to change the component values for different input and output
impedance levels. Do not use very high impedance probes; they represent a heavy capacitive load to the
amplifier and will alter their response. Instead, use low-impedance (
≤
500
Ω
) probes with adequate
bandwidth. The probe input capacitance and resistance set an upper limit on the measurement bandwidth.
If a high-impedance probe must be used, place a 100
Ω
resistor on the probe tip to isolate its capacitance
from the circuit.
3
SBOU044C – April 2007 – Revised April 2015
DEM-OPA-MSOP-1B Demonstration Fixture
Copyright © 2007–2015, Texas Instruments Incorporated
