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3.5

Optional Signal Conditioning Op-Amp (U4B)

3.6

Jumper Settings

EVM Operation

3.4.3

Capacitive Load Drive

It may be required to drive a wide range of capacitive loads. However, under certain conditions, all op
amps may become unstable, depending on the op amp configuration, gain, and load value. These factors
are just few of the issues that can affect op amp stability and should be considered during implementation.

In unity gain configuration, the OPA627 op amp (U2) performs very well with very large capacitive loads.
Increasing the gain enhances amplifier ability to drive even more capacitance, and adding a load resistor
even improves the capacitive load drive capability.

Table 6

shows the jumper setting configuration for a capacitive load drive.

Table 6. Capacitive Load Drive Output Jumper Settings

Jumper Setting

Reference

Unipolar

Bipolar

Function

V

REF

H is disconnected from the inverting input of

JMP5

Open

Open

the output op amp U2.

Supplies power, V

SS

, to the negative rail of op amp

JMP10

2-3

1-2

U2 for bipolar mode, or ties it to AGND for unipolar
mode.

Capacitive load drive output of DAC is routed to pin

JMP6

Open

Open

2 of JMP6 and may be used as the output terminal.

One half of the OPA2132 dual package op amp (U4) is used for reference buffering (U4A), while the other
half is unused. This unused op amp (U4B) is left for whatever op amp circuit application the user desires
to implement. The 1206 footprint for the resistors and capacitors surrounding the U4B op amp are not
populated and are made available for easy configuration. Test points TP5 and TP6 are not installed, so it
is up to the user on how to connect the (

±

) input signals to this op amp. No test point has been made

available for the output because of space restrictions, but a wire can be soldered to the output of the op
amp via an unused component pad that connects to it. The op amp circuit can be configured by populating
the corresponding components to those that match the circuit design while leaving all other unused
component footprints unpopulated.

Table 7

shows the function of each specific jumper setting of the EVM.

Table 7. Jumper Settings and Functions

Reference

Jumper Setting

(1)

Function

EN pin is set high through pull-up resistor R1. EN can be driven by
GPIO2, J2-8.

JMP1

EN pin is set low and DAC is enabled.

LDAC pin is set high through pull-up resistor R2. LDAC can be driven by
GPIO0, J2-2.

JMP2

LDAC pin is set low and DAC update is accomplished via software.

A1 pin is set high through pull-up resistor R3. A1 can be driven by GPIO4,
J2-14.

JMP3

A1 pin is set low.

(1)

Indicates the corresponding pins that are shorted or closed.

SBAU121 – January 2006

DAC8554EVM User's Guide

17

Summary of Contents for DAC8554EVM

Page 1: ...sign and Performance 4 3 EVM Operation 14 4 Schematic 20 List of Figures 1 DAC8554EVM Functional Block Diagram 3 2 DAC8554EVM PCB Top Silkscreen Image 5 3 DAC8554EVM PCB Layer 1 Top Signal Layer 5 4 D...

Page 2: ...l section are powered by 5V VDD The VCC supply source is primarily used to provide the positive rail of the external output op amp U2 the reference chip U3 and the reference buffer U4 The negative rai...

Page 3: ...the trouble involved with building a custom cable Additionally there is also an MSP430 based platform HPA449 that uses the MSP430F449 microprocessor to which this EVM can connect and interface as wel...

Page 4: ...ement and proper signal routing Place the bypass capacitors as close as possible to the device pins and properly separate the analog and digital signals from each other In the layout process carefully...

Page 5: ...www ti com PCB Design and Performance Figure 2 DAC8554EVM PCB Top Silkscreen Image Figure 3 DAC8554EVM PCB Layer 1 Top Signal Layer SBAU121 January 2006 DAC8554EVM User s Guide 5...

Page 6: ...www ti com PCB Design and Performance Figure 4 DAC8554EVM PCB Layer 2 Ground Plane Figure 5 DAC8554EVM PCB Layer 3 Power Plane DAC8554EVM User s Guide 6 SBAU121 January 2006...

Page 7: ...www ti com PCB Design and Performance Figure 6 DAC8554EVM PCB Layer 4 Bottom Signal Layer Figure 7 DAC8554EVM PCB Bottom Silkscreen Image SBAU121 January 2006 DAC8554EVM User s Guide 7...

Page 8: ...1 Minimum copper conductor width is 7 mils Minimum conductor spacing is 7 mils 12 Number of finished layers 4 13 Board dimensions 3 250 in x 1 7 in 50 15mil 0 381 mm PTH 43 23 622mil 0 6mm PTH 42 39 3...

Page 9: ...www ti com PCB Design and Performance Figure 9 INL and DNL Characterization Graph of DAC A SBAU121 January 2006 DAC8554EVM User s Guide 9...

Page 10: ...www ti com PCB Design and Performance Figure 10 INL and DNL Characterization Graph of DAC B DAC8554EVM User s Guide 10 SBAU121 January 2006...

Page 11: ...www ti com PCB Design and Performance Figure 11 INL and DNL Characterization Graph of DAC C SBAU121 January 2006 DAC8554EVM User s Guide 11...

Page 12: ...www ti com PCB Design and Performance Figure 12 INL and DNL Characterization Graph of DAC D 12 DAC8554EVM User s Guide SBAU121 January 2006...

Page 13: ...05 X7R 10 3 C1 C2 C3 TDK C3216X7R1C106M Multilayer Ceramic Capacitor 10 F 1206 X7R Not 2 C8 C9 TDK Multilayer Ceramic Capacitor 1206 Installed 16 bit Quad Voltage Output Serial Input DAC 11 1 U1 Texas...

Page 14: ...4 1 is connected to the noninverting input of the output op amp U2 JMP16 1 2 J4 5 is connected to the output of the op amp U2 The host processor drives the DAC Thus proper DAC operation depends on a s...

Page 15: ...channels when stacking two EVMs together The DAC8554EVM includes an optional signal conditioning circuit for the DAC output through an external operational amplifier U2 The output op amp is set to uni...

Page 16: ...pen resistor R9 3 4 2 Output Gain of 2 There are two types of configurations that will yield an output gain of 2 depending on the setup of jumpers JMP5 and JMP6 These configurations allow the user to...

Page 17: ...U4 is used for reference buffering U4A while the other half is unused This unused op amp U4B is left for whatever op amp circuit application the user desires to implement The 1206 footprint for the re...

Page 18: ...9 for output gain of 2 5V analog supply is selected for AVDD JMP7 3 3V analog supply is selected for AVDD Routes the adjustable buffered onboard 5V reference to the VREFH input of the DAC8554 JMP8 Rou...

Page 19: ...Function Routes VOUTB to J4 4 JMP12 Routes VOUTB to J4 12 Routes VOUTC to J4 6 JMP13 Routes VOUTC to J4 14 Routes VOUTD to J4 8 JMP14 Routes VOUTD to J4 16 Routes J4 1 to U2 noninverting input JMP15 R...

Page 20: ...www ti com 4 Schematic Schematic DAC8554EVM User s Guide 20 SBAU121 January 2006...

Page 21: ...DVDD 12 LDAC 16 A1 14 GND 6 VrefH 3 VrefL 5 VoutA 1 ENABLE 15 A0 13 VoutD 8 Din 11 SCLK 10 SYNC 9 AVDD 4 VoutC 7 U1 DAC8554IPW A0 2 A1 4 A2 6 A3 8 A4 10 A5 12 A6 14 A7 16 REF 18 REF 20 A0 1 A1 3 A2 5...

Page 22: ...proceeding User assumes all responsibility and liability for proper and safe handling and use of the EVM and the evaluation of the EVM TI shall have no liability for any costs losses or damages result...

Page 23: ...ute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual pro...

Page 24: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments DAC8554EVM...

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