Texas Instruments DAC8534 User Manual Download Page 27

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2

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B

C

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Revision History

REV

ECN Number

Approved

DAC8534 RevA.Sch

DOCUMENTCONTROL #

C1

0.1µF

C2

0.1µF

+5VA

SCLK

R6

10K

VSS

2

3

6

4

7

1

5

U2

Op Amp

VCC

C10

1µF

C9

1µF

R12
10K

C12

1nF

W5

R8

0

GND

4

TRIM

5

NC

1

NC

7

NC

8

TEMP

3

OUT

6

V+

2

U3

REF02AU(8)

C11

10µF

C3

0.1µF

VCC

1

3

TP1

TP2

EXTERNAL

REFERENCE

1

2

3

R11

100K

R10

20K

1

2

3

R9

20K

VCC

VDD

VDD

W4

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

J4

OUTPUT HEADER

VrefH

FSX

C6

10µF

C5

10µF

DAC8534_74 EVM

A

J. PARGUIAN

W7

W10

W8

VSS

+REFin

+REFin

W9

Tantalum

1

SDI

CLKX

DX

CLKR

FSR

DR

VoutB

2

IO_V/DVDD

12

A3/LDAC

16

A1

14

GND

6

VrefH

3

VrefL

5

VoutA

1

A2/EN

15

A0

13

VoutD

8

SDA/Din

11

SCL/SCLK

10

LDAC/SYNC

9

AVDD

4

VoutC

7

U1

DAC7574/8534/8574

VDD

R15 440/0

R16 440/0

R5

3K

R7

3K

R1

10K

R2

10K

R3

10K

R4

10K

-REFin

W2

OUT_A1

OUT_C1

OUT_B1

OUT_D1

OUT_A2

OUT_B2

OUT_C2

OUT_D2

OUT_A

OUT_B

OUT_C

OUT_D

2

3

1

8

4

U8A
OPA2227UA

5

6

7

U8B

OPA2227UA

R17
0

TP5

-REFin

VrefH

R14

10K

Vr

ef

H

VCC

C7

0.1µF

TP3

VOUT

U2_+IN

U2_-IN

U2_OUT

VrefL

1

2

3

4

5

6

7

8

9

10

11 12

13 14

15 16

20

17

19

18

J2

Serial Header

W6

VrefL

TP4

R23

NI

R22

NI

R21

NI

R20

NI

R24

NI

C13

NI

C8

NI

R19

NI

R18

NI

VCC = +15V Analog
VDD = +2.7V to +5.0V Digital
VSS = 0V to -15V Analog

TP6

+Vin

TP7

-Vin

1

2

3

J1

1

2

3

J5

+5VA

NOTE:  Voltage range of -REFin input should not exceed
 0 - VrefH.

VCC

1

2

3

4

5

6

7

8

9

10

J6

VSS

+5VA

-5VA

VDD

+3.3VD+1.8VD

+3.3VA

GPIO0

GPIO1

SCL

SDA

R25

0

R26

0

GPIO2

GPIO3

GPIO0

GPIO1

GPIO2

GPIO3

R27

0

R28

0

GPIO4

GPIO5

GPIO4

GPIO5

R31

0

R32

0

R33

0

R29

0
R30
0

FSX

GPIO0

(LDAC)

(LDAC)

(SYNC)

(A3)

(EN)

(A2)

(A1)

(A0)

(LDAC)

(A3)
(EN)

(A2)
(A1)

(A0)

R34

0
R35

0

SCLK

SDI

R36

0

R37

0

DX

CLKX

R38

0

R39

0

W1

+3.3VA

AVDD

W11

W12

W13

6447711

R13

100

W15

W3

Summary of Contents for DAC8534

Page 1: ...DAC8534 Evaluation Module June 2003 Data Acqusition Digital Analog Converters User s Guide SLAU107...

Page 2: ...itute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual p...

Page 3: ...handling or use of the goods Please be aware that the products received may not be regulatory compliant or agency certified FCC UL CE etc Due to the open construction of the product it is the user s r...

Page 4: ...here is uncertainty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 60 C The EVM is design...

Page 5: ...and circuit descriptions are included How to Use This Manual This document contains the following chapters Chapter 1 EVM Overview Chapter 2 PCB Design and Performance Chapter 3 EVM Operation Informati...

Page 6: ...struments Data Converter evaluation modules please feel free to e mail the Data Converter Application Team at dataconvapps list ti com Include in the subject heading the product you have questions or...

Page 7: ...ance 2 1 2 1 PCB Layout 2 2 2 2 EVM Performance 2 3 2 3 Bill of Materials 2 4 3 EVM Operation 3 1 3 1 Factory Default Setting 3 2 3 2 Host Processor Interface 3 2 3 3 EVM Stacking 3 3 3 4 The Output O...

Page 8: ...2 2 2 5 Layer 4 Bottom Signal Plane 2 2 2 6 Bottom Silkscreen 2 2 2 7 Drill Drawing 2 2 Tables 2 1 Parts List 2 4 3 1 Factory Default Jumper Setting 3 2 3 2 DAC Output Channel Mapping 3 3 3 3 Unity Ga...

Page 9: ...pter gives a general overview of the DAC8534 evaluation module EVM and describes some of the factors that must be considered in using this module Topic Page 1 1 Features 1 2 1 2 Power Requirements 1 2...

Page 10: ...inals The device under test U1 can be powered by connecting an analog power supply at terminal 5 VA or 3 3 VA and selecting the proper position of jumper W1 This allows the DAC8534 analog section to o...

Page 11: ...a host processor or waveform generator to the DAC8534 EVM using a custom built cable A specific adapter interface card is also available for most of TI s DSP starter kits DSK card models depend on the...

Page 12: ...dule Output Buffer Module VCC VSS VCC GND GND VDD DAC Out 4 CH J1 J5 J6 P6 External Reference Module VDD J2 P2 A0 A1 SYNC SCLK LDAC TP2 W4 TP1 VSS DIN W2 W11 W12 W13 J4 P4 8 CH TP3 EN A0 A1 TP5 W6 W8...

Page 13: ...bes the layout design and mechanical characteristics of the PCB as well as a brief description of the EVM test performance procedure The EVM bill of materials is also included in this section Topic Pa...

Page 14: ...arated from each other The power and ground plane is very important and should be carefully considered in the layout process A solid plane is ideally preferred but sometimes impractical so when solid...

Page 15: ...PCB Layout 2 3 PCB Design and Performance Figure 2 1 Top Silkscreen Figure 2 2 Layer 1 Top Signal Plane Figure 2 3 Layer Two Ground Plane...

Page 16: ...PCB Layout 2 4 Figure 2 4 Layer 3 Power Plane Figure 2 5 Layer 4 Bottom Signal Plane Figure 2 6 Bottom Silkscreen...

Page 17: ...using a high density DAC bench test board an Agilent 3458A digital multimeter and a PC running the LABVIEW software The EVM board is tested for all codes of 65535 and the device under test DUT is allo...

Page 18: ...TSM 105 01 T DV 5X2X0 1 10 pin 3A isolated power socket 13 2 J2 J4 Samtec TSM 110 01 S DV M 10X2X 1 20 Pin 0 025 sq SMT socket 14 2 J1 J5 On Shore Technology ED555 3DS 3 Pin terminal connector 15 1 U1...

Page 19: ...r to the DAC8534 data sheet SBAS254 for information about its serial interface and other related topics The EVM board is factory tested and configured to operate in the bipolar output mode Topic Page...

Page 20: ...ut op amp U2 is configured for a gain of 2 J4 2 1 DAC output A VOUTA is connected to the noninverting input of the output op amp U2 3 2 Host Processor Interface The host processor basically drives the...

Page 21: ...ignal of the first EVM through GPIO2 P2 J2 pin 8 populating R27 and disconnecting R28 The second EVM should use the GPIO3 P2 J2 pin12 for enable signal routing Also populate R28 and disconnect R27 The...

Page 22: ...REFH as an offset or not Table 3 4 shows the proper jumper settings of the EVM for the 2 gain output of the DAC Table 3 4 Gain of Two Output Jumper Settings Jumper Setting Reference Unipolar Bipolar F...

Page 23: ...ual package op amp OPA2132 U8 is used for reference buffering U8A while the other is unused This unused op amp U8B is available for whatever op amp circuit application the user desires to implement Th...

Page 24: ...e supply rail of the output op amp U2 is powered by VSS for bipolar operation W5 1 3 Negative supply rail of the output op amp U2 is tied to AGND for unipolar operation 1 3 VREFL is tied to AGND W6 1...

Page 25: ...2 1 3 Routes VOUTC to J4 14 1 3 Routes VOUTD to J4 8 W13 1 3 Routes VOUTD to J4 16 Disconnects the inverting input of the output op amp U2 from AGND W15 Connects the inverting input of the output op a...

Page 26: ...Schematic 3 8 3 7 Schematic A 17 X11 schematic diagram is an attachment to this document...

Page 27: ...AC SYNC 9 AVDD 4 VoutC 7 U1 DAC7574 8534 8574 VDD R15 440 0 R16 440 0 R5 3K R7 3K R1 10K R2 10K R3 10K R4 10K REFin W2 OUT_A1 OUT_C1 OUT_B1 OUT_D1 OUT_A2 OUT_B2 OUT_C2 OUT_D2 OUT_A OUT_B OUT_C OUT_D 2...

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