Texas Instruments DAC8534 User Manual Download Page 23

Optional Signal Conditioning Op Amp (U8B)

3-5

EVM Operation

even more capacitance, and by adding a load resistor even improves the
capacitive load drive capability.

Table 3 - 5. Capacitive Load Drive Ouptut Jumper Settings

Jumper Setting

Reference

Unipolar

Bipolar

Function

W3

Open

Open

V

REF

H is disconnected from the inverting input of the output op amp, U2.

W5

2 - 3

1 - 2

Supplies V

SS

 power  to the negative rail of op amp U2 for bipolar mode,

or ties it to AGND for unipolar mode.

W15

Open

Open

Capacitive load drive output of DAC is routed to pin 1 of W15 jumper,  and
may be used as the output terminal.

3.5

Optional Signal Conditioning Op Amp (U8B)

One part of the dual package op amp, OPA2132 (U8), is used for reference
buffering (U8A) while the other is unused. This unused op amp (U8B) is
available for whatever op amp circuit application the user desires to
implement. The 1206 footprint for the resistors and capacitors surrounding the
U8B op amp are not populated, but are available for easy configuration. TP6
and TP7 test points are also not installed, so it is up to the user as to how to
connect the 

±

 input signals to this op amp. No test point is available for the

output due to space restriction, but a wire can be simply soldered to the output
of the op amp via unused component pads connected to it.

Once the op amp circuit design is realized, configuring the EVM becomes easy
by simply populating the corresponding components that match the circuit
design, and leaving all other unneeded component footprints unpopulated.

Summary of Contents for DAC8534

Page 1: ...DAC8534 Evaluation Module June 2003 Data Acqusition Digital Analog Converters User s Guide SLAU107...

Page 2: ...itute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual p...

Page 3: ...handling or use of the goods Please be aware that the products received may not be regulatory compliant or agency certified FCC UL CE etc Due to the open construction of the product it is the user s r...

Page 4: ...here is uncertainty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 60 C The EVM is design...

Page 5: ...and circuit descriptions are included How to Use This Manual This document contains the following chapters Chapter 1 EVM Overview Chapter 2 PCB Design and Performance Chapter 3 EVM Operation Informati...

Page 6: ...struments Data Converter evaluation modules please feel free to e mail the Data Converter Application Team at dataconvapps list ti com Include in the subject heading the product you have questions or...

Page 7: ...ance 2 1 2 1 PCB Layout 2 2 2 2 EVM Performance 2 3 2 3 Bill of Materials 2 4 3 EVM Operation 3 1 3 1 Factory Default Setting 3 2 3 2 Host Processor Interface 3 2 3 3 EVM Stacking 3 3 3 4 The Output O...

Page 8: ...2 2 2 5 Layer 4 Bottom Signal Plane 2 2 2 6 Bottom Silkscreen 2 2 2 7 Drill Drawing 2 2 Tables 2 1 Parts List 2 4 3 1 Factory Default Jumper Setting 3 2 3 2 DAC Output Channel Mapping 3 3 3 3 Unity Ga...

Page 9: ...pter gives a general overview of the DAC8534 evaluation module EVM and describes some of the factors that must be considered in using this module Topic Page 1 1 Features 1 2 1 2 Power Requirements 1 2...

Page 10: ...inals The device under test U1 can be powered by connecting an analog power supply at terminal 5 VA or 3 3 VA and selecting the proper position of jumper W1 This allows the DAC8534 analog section to o...

Page 11: ...a host processor or waveform generator to the DAC8534 EVM using a custom built cable A specific adapter interface card is also available for most of TI s DSP starter kits DSK card models depend on the...

Page 12: ...dule Output Buffer Module VCC VSS VCC GND GND VDD DAC Out 4 CH J1 J5 J6 P6 External Reference Module VDD J2 P2 A0 A1 SYNC SCLK LDAC TP2 W4 TP1 VSS DIN W2 W11 W12 W13 J4 P4 8 CH TP3 EN A0 A1 TP5 W6 W8...

Page 13: ...bes the layout design and mechanical characteristics of the PCB as well as a brief description of the EVM test performance procedure The EVM bill of materials is also included in this section Topic Pa...

Page 14: ...arated from each other The power and ground plane is very important and should be carefully considered in the layout process A solid plane is ideally preferred but sometimes impractical so when solid...

Page 15: ...PCB Layout 2 3 PCB Design and Performance Figure 2 1 Top Silkscreen Figure 2 2 Layer 1 Top Signal Plane Figure 2 3 Layer Two Ground Plane...

Page 16: ...PCB Layout 2 4 Figure 2 4 Layer 3 Power Plane Figure 2 5 Layer 4 Bottom Signal Plane Figure 2 6 Bottom Silkscreen...

Page 17: ...using a high density DAC bench test board an Agilent 3458A digital multimeter and a PC running the LABVIEW software The EVM board is tested for all codes of 65535 and the device under test DUT is allo...

Page 18: ...TSM 105 01 T DV 5X2X0 1 10 pin 3A isolated power socket 13 2 J2 J4 Samtec TSM 110 01 S DV M 10X2X 1 20 Pin 0 025 sq SMT socket 14 2 J1 J5 On Shore Technology ED555 3DS 3 Pin terminal connector 15 1 U1...

Page 19: ...r to the DAC8534 data sheet SBAS254 for information about its serial interface and other related topics The EVM board is factory tested and configured to operate in the bipolar output mode Topic Page...

Page 20: ...ut op amp U2 is configured for a gain of 2 J4 2 1 DAC output A VOUTA is connected to the noninverting input of the output op amp U2 3 2 Host Processor Interface The host processor basically drives the...

Page 21: ...ignal of the first EVM through GPIO2 P2 J2 pin 8 populating R27 and disconnecting R28 The second EVM should use the GPIO3 P2 J2 pin12 for enable signal routing Also populate R28 and disconnect R27 The...

Page 22: ...REFH as an offset or not Table 3 4 shows the proper jumper settings of the EVM for the 2 gain output of the DAC Table 3 4 Gain of Two Output Jumper Settings Jumper Setting Reference Unipolar Bipolar F...

Page 23: ...ual package op amp OPA2132 U8 is used for reference buffering U8A while the other is unused This unused op amp U8B is available for whatever op amp circuit application the user desires to implement Th...

Page 24: ...e supply rail of the output op amp U2 is powered by VSS for bipolar operation W5 1 3 Negative supply rail of the output op amp U2 is tied to AGND for unipolar operation 1 3 VREFL is tied to AGND W6 1...

Page 25: ...2 1 3 Routes VOUTC to J4 14 1 3 Routes VOUTD to J4 8 W13 1 3 Routes VOUTD to J4 16 Disconnects the inverting input of the output op amp U2 from AGND W15 Connects the inverting input of the output op a...

Page 26: ...Schematic 3 8 3 7 Schematic A 17 X11 schematic diagram is an attachment to this document...

Page 27: ...AC SYNC 9 AVDD 4 VoutC 7 U1 DAC7574 8534 8574 VDD R15 440 0 R16 440 0 R5 3K R7 3K R1 10K R2 10K R3 10K R4 10K REFin W2 OUT_A1 OUT_C1 OUT_B1 OUT_D1 OUT_A2 OUT_B2 OUT_C2 OUT_D2 OUT_A OUT_B OUT_C OUT_D 2...

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