Circuit Function
3-2
3.1
Circuit Function
The following paragraphs describe the EVM circuits.
3.1.1
Input Clock
The DAC5674 EVM default operation setting is with a differential input clock
sent to the DAC5674. A 500-mV p-p, 0-V offset, 50% duty-cycle external
sinewave is applied to SMA connector J4 and converted to a differential clock
input to the DAC5674 by transformer T2. This input represents a 50-
Ω
load to
the source. In order to preserve the specified performance of the DAC5674
converter, the clock source should feature very low jitter. Using a clock with a
50% duty cycle gives optimum dynamic performance.
3.1.1.1
Differential ECL/PECL Input Clock
The EVM can be configured for differential ECL/PECL input clock mode by
configuring the board per Table 3−1 and applying the appropriate ECL/PECL
common mode voltage at terminal E1 (VTT). Use J3 and J5 to input the
external differential ECL/PECL clock signals.
3.1.1.2
Single-Ended Input Clock
The EVM can be configured for single-ended input clock mode by configuring
the board per Table 3−1. SMA connector J3 or header J8 can be used to input
the external TTL/CMOS clock signal.
Table 3−1. EVM Clock Configuration
Clock Configuration
Components Installed
†
Components Not Installed
Sinewave (Default)
R12, T2, C52
R9, R10, R34, R35, R36, R37,
C55, C56
ECL or PECL
R9 (0.01-
µ
F cap.), R10 (0.01-
µ
F
cap.)
R36, R12, R34, R35, R37, T2,
C55, C56
Single ended TTL/CMOS from J3
R9, C55
R10, R12, R25, R34, R35, R37,
T2, C56
Single ended TTL/CMOS from J8
R34, R37, C55
R9, R10, R12, R35, T2, C56
†
All component values are per the schematic except where shown in parentheses.
3.1.2
Input Data
The DAC5674 EVM can accept 3.3-V CMOS logic level data inputs through
the 40-pin header J8 per Table 3−2. The board provides 50-
Ω
termination to
ground and series dampening resistors to minimize digital ringing and
switching noise. J8 also provides a path for an input clock (see Table 3−1 for
proper board configuration).
