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4.2 DAC53701EVM Schematic
WP
A0
1
A1
2
A2
3
VSS
4
SDA
5
SCL
6
WP
7
VCC
8
U3
BR24G32FVT-3AGE2
BOOSTXL-DAC-PORT Interface Left
BOOSTXL-DAC-PORT Interface Right
VDD
GND
GND
NT9
Net-Tie
REFGND
GND
25V
0.1uF
C1
VIO
GND
GND
GND
25V
0.1uF
C5
10.0k
R12
10.0k
R15
5
4
1
2
3
6
7
8
9
10
11
12
13
14
15
16
J2
5
4
1
2
3
6
7
8
9
10
11
12
13
14
15
16
J1
SCL
REF
VDD
NT10
Net-Tie
AGND
GND
VIO
NT1
Net-Tie
NT2
Net-Tie
NT3
Net-Tie
NT5
Net-Tie
NT4
Net-Tie
NT6
Net-Tie
NT7
Net-Tie
NT8
Net-Tie
AGND
AGND
SDA
VOUT
VFB
SCL
SDA
10.0k
R10
10.0k
R17
VIO
GND
10.0k
R9
10.0k
R16
VIO
GND
10.0k
R11
10.0k
R18
VIO
GND
VCCA
1
SCLA
2
SDAA
3
GND
4
EN
5
SDAB
6
SCLB
7
VCCB
8
TCA9800DGKR
U2
VIO
DAC_VIO
DAC_VIO
DAC_VIO
GND
SDA
SCL
DAC_SDA
DAC_SCL
10.0k
R6
10.0k
R7
VIO
25V
0.1uF
C3
GND
25V
0.1uF
C4
GND
10.0k
R8
GND
0
R13
0
R14
SDA
SCL
DAC_SDA
DAC_SCL
REFGND
VDD
6
VSS
5
VFB
7
VOUT
8
SCL
2
GPI
1
SDA
3
LDO_CAP
4
EP
9
U1
DAC53701DSG
10V
2.2uF
C2
GND
10.0k
R3
GND
0
R2
DAC_VIO
LDO_CAP
LDO_CAP
10.0k
R1
DAC_SCL
DAC_SDA
DAC_GPI
DAC_GPI
This buffer is disabled by default
due to absense of VIO
Pull-ups are not recommended
on B side of the buffer
Option for force-sense
connection
Figure 4-3. DAC53701EVM Schematic
Schematic, PCB Layout, and Bill of Materials
SLAU841 – OCTOBER 2020
DAC53701EVM
25
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