Quick Start
8
SLAU671A – October 2016 – Revised March 2017
Copyright © 2016–2017, Texas Instruments Incorporated
DAC38RF8xEVM
8. Click on the
Reset DAC JESD Core
button and the
Trigger LMK04828 SYSREF
button.
2.1.4
DAC38RF8xEVM Configuration With On-Chip PLL(CMODE3)
Skip this section if using an external clock such as the DAC clock source.
NOTE:
The 2-pin jumper labeled JP10 must be open to enable on-chip PLL clock mode. This is
shown in
. Other hardware changes may be required depending on the on-chip PLL
clocking mode selected. These changes are described in
Figure 6. Open Pin 1 and Pin 2 of JP10 Jumper to Enable On-Chip PLL Clock Mode
