Amplitude Unbalance
Phase Unbalance
Frequency (MHz)
Frequency (MHz)
Frequency (MHz)
Frequency (MHz)
In
se
rt
io
n
L
o
ss
(d
b
)
Average Insertion Loss
Input Return Loss
Amp
lit
u
d
e
U
n
b
a
la
n
ce
(
d
b
)
Ph
a
se
U
n
b
a
la
n
ce
(
d
e
g
)
In
p
u
t
R
e
tu
rn
L
o
ss
(d
B
)
18
SLAU671A – October 2016 – Revised March 2017
Copyright © 2016–2017, Texas Instruments Incorporated
Appendix B
SLAU671A – October 2016 – Revised March 2017
B.1
Clock Balun Characteristics
illustrates the clock input path circuit schematic.
Figure 20. Clock Input Path Circuit Diagram
Figure 21. NCR2-113+ Frequency Response
