Texas Instruments Concerto F28M36 Series, Technical Reference Manual

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C-Boot ROM Description
637 SPRUHE8E – October 2012 – Revised November 2019
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Copyright © 2012–2019, Texas Instruments Incorporated
ROM Code and Peripheral Booting
Table 6-23. C-Boot ROM Exceptions Handling
Exception Event Source Description C-Boot ROM action C-Boot ROM state after
exception
CLOCKFAIL – from missing
clock detection logic CLKFAIL condition detected cbrom_handle_nmi :-> Clear
NMI Flags, Save error status in
CTOMBOOTSTS register bits
and returns from the interrupt
handler.
NMI is generated to the master
subsystem also, No IPC
message is sent. Continue to boot, because
missing clock circuit will switch
CPU to 10 MHz clock source
M3BISTERR M3 HW BIST Error NMI Flag Default NMI HANDLER:->
Clear NMI Flags, Save error
status in CTOMBOOTSTS
register bits and wait in
while(1) loop for master to
handle the error state. NMI is
generated to C28 also, so no
need to send an IPC message. Wait in While(1) loop, for reset
from master.
C28BISTERR C28 HW BIST Error NMI Flag Default NMI HANDLER:->
Clear NMI Flags, Save error
status in CTOMBOOTSTS
register bits and wait in
while(1) loop for master to
handle the error state. NMI is
generated to M3 also, so no
need to send an IPC message. Wait in While(1) loop, for reset
from master.
C28RAMUNCERR C28 RAM Uncorrectable Error
NMI Flag cbrom_handle_nmi :-> Clear
NMI Flags, Save error status in
CTOMBOOTSTS register,
send IPC message to master
and wait in while(1) loop for
master to handle the error
state.. Wait in While(1) loop, for reset
frommaster.
C28FLUNCERR C28 Flash Uncorrectable Error
NMI cbrom_handle_nmi :-> Clear
NMI Flags, Save error status in
CTOMBOOTSTS register,
send IPC message to master
and wait in while(1) loop for
master to handle the error state Wait in While(1) loop, for reset
frommaster.
ACIBERR CIB Error NMI Flag cbrom_handle_nmi :-> Clear
NMI Flags, Save error status in
CTOMBOOTSTS register bits
and wait in while(1) loop for
master to handle the error
state.
NMI is generated to M3 also,
so no need to send an IPC
message. Wait in While(1) loop, for reset
from master.
ILLEGAL ITRAP exception cbrom_itrap_isr :-> IPC
Message is sent to master and
iTrap address is written to
CTOMIPCADDR.
CTOMBOOTSTS register is set
to reflect the error status and
wait in while(1) loop for master
to handle the error state. Wait in While(1) loop, for reset
frommaster.
PIE VECTOR ADDRESS
MISMATCH PIE vector fetch mismatch
handler at 0x3FFFBE Update CTOMBOOTSTS to
reflect the error, and the ROM
handler @0x3FFFBE will send
an IPC message to master and
wait in while(1) loop for master
to handle the error state. Wait in While(1) loop, for reset
from master.