Texas Instruments Concerto F28M36 Series, Technical Reference Manual

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Host Bus Mode
1239 SPRUHE8E – October 2012 – Revised November 2019
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Copyright © 2012–2019, Texas Instruments Incorporated
External Peripheral Interface (EPI)
(1)
If the CSBAUD bit in the EPIHBnCFG2 register is clear and multiple chip selects are enabled, then all chip selects are
configured by the MODE bit field in the EPIHBnCFG register.
Table 17-4. Chip Select Configuration Register Assignment
Configuration Register
(1)
Corresponding Chip Select
EPIHBnCFG CS0
EPIHBnCFG2 CS1
EPIHBnCFG3 CS2
EPIHBnCFG4 CS3
Note that multiple chip select modes do not allow the intermixing of Host-Bus 8 and Host-Bus16 modes.
When BSEL=1 in the EPIHB16CFG register, byte select signals are provided, so byte-sized data can be
read and written at any address; however, these signals reduce the available address width by two pins.
The byte select signals are active Low. BSEL0 corresponds to the LSB of the halfword, and BSEL1
corresponds to the MSB of the halfword.
When BSEL=0, byte reads and writes at odd addresses only act on the even byte, and byte writes at even
addresses write invalid values into the odd byte. As a result, accesses should be made as half-words (16-
bits) or words (32-bits). In C/C++, programmers should use only short int and long int for accesses. Also,
because data accesses in HB16 mode with no byte selects are on 2-byte boundaries, the available
address space is doubled. For example, 28 bits of address accesses 512 MB in this mode.
Table 17-5
shows the capabilities of the HB8 and HB16 modes as well as the available address bits with the possible
combinations of these bits.
Although the EPI0S31 signal can be configured for the EPI clock signal in Host-Bus mode, it is not
required and should be configured as a GPIO to reduce EMI in the system.
(1)
If byte selects are not used, data accesses are on 2-byte boundaries. As a result, the available address space is doubled.
(2)
Two EPI signals are used for byte selects, reducing the available address space by two bits.
Table 17-5. Capabilities of Host Bus 8 and Host Bus 16 Modes
Host Bus
Type
Mode CSCFGEXT CSCFG Max # of
External
Devices
BSEL Byte
Access
Available
Address
Addressabl
e Memory
HB8 0x0 0 0x0,0x1 1 N/A Always 28 256 MB
HB8 0x0 0 0x2 2 N/A Always 27 128 MB
HB8 0x0 0 0x3 2 N/A Always 26 64 MB
HB8 0x0 1 0x0 1 N/A Always 27 128 MB
HB8 0x0 1 0x1 4 N/A Always 27 128 MB
HB8 0x0 1 0x2 4 N/A Always 26 64 MB
HB8 0x1 0 0x0,0x1 1 N/A Always 20 1 MB
HB8 0x1 0 0x2 2 N/A Always 19 512 KB
HB8 0x1 0 0x3 2 N/A Always 18 256 KB
HB8 0x1 1 0x0 1 N/A Always 19 512 MB
HB8 0x1 1 0x1 4 N/A Always 19 512 MB
HB8 0x1 1 0x2 4 N/A Always 18 256 MB
HB8 0x3 X X - N/A Always None -
HB16 0x0 0 0x0,0x1 1 0 No 28
(1)
512 MB
HB16 0x0 0 0x0,0x1 1 1 Yes 26
(2)
64 MB
HB16 0x0 0 0x2 2 0 No 27
(1)
256 MB
HB16 0x0 0 0x2 2 1 Yes 25
(2)
32 MB
HB16 0x0 0 0x3 2 0 No 26
(1)
128 MB
HB16 0x0 0 0x3 2 1 Yes 24
(2)
16 MB
HB16 0x0 1 0x0 1 0 No 27
(1)
256 MB
HB16 0x0 1 0x0 1 1 Yes 25
(2)
32 MB
HB16 0x0 1 0x1 4 0 No 27
(1)
256 MB