SPI Operation Using the Clock Stop Mode
1110
SPRUHE8E – October 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
C28 Multichannel Buffered Serial Port (McBSP)
Table 15-14. Bits Used to Enable and Configure the Clock Stop Mode (continued)
Bit Field
Description
XPHASE bit of XCR2
You must use a single-phase transmit frame (XPHASE = 0).
RPHASE bit of RCR2
You must use a single-phase receive frame (RPHASE = 0).
XFRLEN1 bits of XCR1
You must use a transmit frame length of 1 serial word (XFRLEN1 = 0).
RFRLEN1 bits of RCR1
You must use a receive frame length of 1 serial word (RFRLEN1 = 0).
XWDLEN1 bits of XCR1
The XWDLEN1 bits determine the transmit packet length. XWDLEN1 must be equal to
RWDLEN1 because in the clock stop mode. The McBSP transmit and receive circuits
are synchronized to a single clock.
RWDLEN1 bits of RCR1
The RWDLEN1 bits determine the receive packet length. RWDLEN1 must be equal to
XWDLEN1 because in the clock stop mode. The McBSP transmit and receive circuits
are synchronized to a single clock.
Table 15-15. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme
Bit Settings
Clock Scheme
CLKSTP = 00b or 01b
Clock stop mode disabled. Clock enabled for non-SPI mode.
CLKXP = 0 or 1
CLKRP = 0 or 1
CLKSTP = 10b
Low inactive state without delay: The McBSP transmits data on the rising edge of CLKX and
receives data on the falling edge of MCLKR.
CLKXP = 0
CLKRP = 0
CLKSTP = 11b
Low inactive state with delay: The McBSP transmits data one-half cycle ahead of the rising
edge of CLKX and receives data on the rising edge of MCLKR.
CLKXP = 0
CLKRP = 1
CLKSTP = 10b
High inactive state without delay: The McBSP transmits data on the falling edge of CLKX and
receives data on the rising edge of MCLKR.
CLKXP = 1
CLKRP = 0
CLKSTP = 11b
High inactive state with delay: The McBSP transmits data one-half cycle ahead of the falling
edge of CLKX and receives data on the falling edge of MCLKR.
CLKXP = 1
CLKRP = 1
15.7.4 Clock Stop Mode Timing Diagrams
The timing diagrams for the four possible clock stop mode configurations are shown here. Notice that the
frame-synchronization signal used in clock stop mode is active throughout the entire transmission as a
slave-enable signal. Although the timing diagrams show 8-bit transfers, the packet length can be set to 8,
12, 16, 20, 24, or 32 bits per packet. The receive packet length is selected with the RWDLEN1 bits of
RCR1, and the transmit packet length is selected with the XWDLEN1 bits of XCR1. For clock stop mode,
the values of RWDLEN1 and XWDLEN1 must be the same because the McBSP transmit and receive
circuits are synchronized to a single clock.
NOTE:
Even if multiple words are consecutively transferred, the CLKX signal is always stopped and
the FSX signal returns to the inactive state after a packet transfer. When consecutive packet
transfers are performed, this leads to a minimum idle time of two bit-periods between each
packet transfer.
