Enhanced SCI Module Overview
990
SPRUH22I – April 2012 – Revised November 2019
Copyright © 2012–2019, Texas Instruments Incorporated
C28 Serial Communications Interface (SCI)
NOTE:
Interrupt generation due to the RXRDY and BRKDT bits is controlled by the RX/BK INT ENA
bit (SCICTL2, bit 1). Interrupt generation due to the RX ERROR bit is controlled by the RX
ERR INT ENA bit (SCICTL1, bit 6).
13.1.1.9 SCI Baud Rate Calculations
The internally generated serial clock is determined by the low-speed peripheral clock LSPCLK) and the
baud-select registers. The SCI uses the 16-bit value of the baud-select registers to select one of the 64K
different serial clock rates possible for a given LSPCLK.
See the bit descriptions in
, for the formula to use when calculating the SCI asynchronous
baud.
shows the baud-select values for common SCI bit rates.
Table 13-5. Asynchronous Baud Register Values for Common SCI Bit Rates
LSPCLK Clock Frequency, 37.5 MHz
Ideal Baud
BRR
Actual Baud
% Error
2400
1952 (7A0h)
2400
0
4800
976 (3D0h)
4798
-0.04
9600
487 (1E7h)
9606
0.06
19200
243 (F3h)
19211
0.06
38400
121 (79h)
38422
0.06
13.1.1.10 SCI Enhanced Features
The 28x SCI features autobaud detection and transmit/receive FIFO. The following section explains the
FIFO operation.
13.1.1.10.1 SCI FIFO Description
The following steps explain the FIFO features and help with programming the SCI with FIFOs.
1.
Reset.
At reset the SCI powers up in standard SCI mode and the FIFO function is disabled. The FIFO
registers SCIFFTX, SCIFFRX, and SCIFFCT remain inactive.
2.
Standard SCI.
The standard F24x SCI modes will work normally with TXINT/RXINT interrupts as the
interrupt source for the module.
3.
FIFO enable.
FIFO mode is enabled by setting the SCIFFEN bit in the SCIFFTX register. SCIRST can
reset the FIFO mode at any stage of its operation.
4. Active registers. All the SCI registers and SCI FIFO registers (SCIFFTX, SCIFFRX, and SCIFFCT) are
active.
5.
Interrupts.
FIFO mode has two interrupts; one for transmit FIFO, TXINT and one for receive FIFO,
RXINT. RXINT is the common interrupt for SCI FIFO receive, receive error, and receive FIFO overflow
conditions. The TXINT of the standard SCI will be disabled and this interrupt will service as SCI
transmit FIFO interrupt.
6.
Buffers.
Transmit and receive buffers are supplemented with two 16-level FIFOs. The transmit FIFO
registers are 8 bits wide and receive FIFO registers are 10 bits wide. The one-word transmit buffer of
the standard SCI, functions as a transition buffer between the transmit FIFO and shift register. The one
word transmit buffer is loaded from transmit FIFO only after the last bit of the shift register is shifted
out. With the FIFO enabled, TXSHF is directly loaded after an optional delay value (SCIFFCT), TXBUF
is not used. When FIFO mode is enabled for SCI, characters written to SCITXBUF are queued in to
SCI-TXFIFO and the characters received in SCI-RXFIFO can be read using SCIRXBUF.
7.
Delayed transfer.
The rate at which words in the FIFO are transferred to the transmit shift register is
programmable. The SCIFFCT register bits (7
−
0) FFTXDLY7
−
FFTXDLY0 define the delay between the
word transfer. The delay is defined in the number SCI baud clock cycles. The 8 bit register can define
a minimum delay of 0 baud clock cycles and a maximum of 256-baud clock cycles. With zero delay,
the SCI module can transmit data in continuous mode with the FIFO words shifting out back to back.
