Texas Instruments CDCM1804 User Manual Download Page 23 | Manualshive

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Schematic

5-5

Schematic, Parts List, Board Stackup, Board Layouts, and References

Figure 5−4. GND1 Layer

Figure 5−5. Bottom Layer

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Summary of Contents for CDCM1804

Page 1: ... 2006 High Performance Analog CDC User s Guide SCAU009C ...

Page 2: ...om TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alterati...

Page 3: ...to take any and all appropriate precautions with regard to electrostatic discharge EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES TI currently deals with a variety of customers for products and therefore our arrangement with the user is not exclusive TI assumes no liability for applicatio...

Page 4: ...nty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 45 C The EVM is designed to operate properly with certain components above 60 C as long as the input and output ranges are maintained These components include but are not limited to linear regulators switching transistors pass transistors...

Page 5: ... recommendations on proper termination decoupling and how to use the CDCM1804 CDCP1803 in single ended applications such as LVTTL LVCMOS or other differential clock signals such as LVPECL LVDS HSTL SSTL 2 CML VML or similar 2 5 V or 3 3 V signals and provide a differential LVPECL output Requesting an EVM Contact your local marketing or sales representative to request a CDCM1804 CDCP1803 EVM How to...

Page 6: ...t to subpart J of part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interference Operation of this equipment in other environments may cause interference with radio communications in which case the user at his own expense will be required to take whatever measures may be required to correct this interference For More Information If you need assitance ...

Page 7: ...CP1803 EVM Configuration 3 1 3 1 Default EVM Delivery 3 2 3 2 Mode Setting for CDCM1804 CDCP1803 Through EN S0 S1 and S2 3 2 4 Using the EVM 4 1 4 1 EVM Power Connections 4 2 4 2 Applying An Input 4 3 4 3 Typical Test Results 4 4 5 Schematic Parts List Board Stack Up Board Layouts and References 5 1 5 1 Schematic 5 2 5 2 Parts List 5 3 5 3 Board Stackup and Layouts 5 4 5 4 References 5 6 ...

Page 8: ...Setup 1 2 4 1 EVM Power Connections for the CDCM1804 CDCP1803 Evaluation 4 2 4 2 Typical Output From the CDCM1804 CDCP1803 EVM 4 4 5 1 Schematic of the EVM Signal Path 5 2 5 2 Top Layer 5 4 5 3 PWR1 Layer 5 4 5 4 GND1 Layer 5 5 5 5 Bottom Layer 5 5 ...

Page 9: ...l translation Both the CDCM1804 and the CDCP1803 can accept single ended signals such as LVTTL or LVCMOS or other differential clock signals such as LVPECL LVDS HSTL SSTL 2 CML and VML or similar 2 5 V or 3 3 V signals and provide a differential LVPECL output The CDCM1804 CDCP1803 are both 3 3 V LVPECL clock drivers CDCM1804 provides three LVPECL one CMOS outputs This evaluation module EVM is desi...

Page 10: ...1 2 Figure 1 1 CDCM1804 CDCP1803 EVM Default Setup ...

Page 11: ... PCB This chapter discusses the use of the EVM and the contents of the kit Topic Page 2 1 Use of the EVM 2 2 2 2 Design of Differential Traces 2 2 2 3 Other Design Tweaks 2 2 2 4 EVM Kit Contents 2 2 Chapter 2 ...

Page 12: ... of a differential signal pair has been matched to maintain 50 Ω line impedance 2 3 Other Design Tweaks In addition the 50 Ω impedance mismatches are reduced by designing the component pad size to be as close as possible to the width of the connecting transmission lines Overall the board layout is designed and optimized to support high speed operation Thus understanding impedance control and trans...

Page 13: ... operates from a 3 3 V supply VT is set to approximately 1 3 V The EVM has been designed to support the various I O signaling and output termination The CDCM1804 CDCP1803 EVM board gives the options for operation some of which can be soldered into the EVM or connected through input connectors Topic Page 3 1 Default EVM Delivery 3 2 3 2 Mode Settings for CDCM1804 CDCP1803 Through EN S0 S1 and S2 3 ...

Page 14: ...gure 3 1 Mode Settings for CDCM1804 CDCP1803 Through EN S0 S1 and S2 3 2 1 Jumper Settings Control input incorporates a 60 kΩ pullup resistor Thus it is easy to choose the input setting by designing a resistor pad between the control input and GND To choose a logic zero the resistor value must be zero Setting the input high requires leaving the resistor pad empty no resistor installed For setting ...

Page 15: ...4 1 Using the EVM This chapter discusses the use of the EVM Topic Page 4 1 EVM Power Connections 4 2 4 2 Applying an Input 4 2 4 3 Typical Test Results 4 2 Chapter 4 ...

Page 16: ...o terminate the LVPECL input As shown in Figure 4 1 the power supply is used to provide the required 3 3 V to the EVM The EVM ground is connected to the oscilloscope ground through the returns on SMA With power applied the common mode voltage seen by the CDCM1804 CDCP1803 is approximately equal to the reference voltage being used inside the device preventing significant common mode current to flow...

Page 17: ...4 3 Using the EVM Figure 4 2 Typical LVPECL Output from the CDCM1804 CDCP1803 EVM ...

Page 18: ...4 4 Figure 4 3 Typical CMOS Output from the CDCM1804 EVM ...

Page 19: ...nd References This appendix contains schematics corresponding parts list board stackup board layout and references for the CDCM1804 CDCP1803 EVM Topic Page 5 1 Schematic 5 2 5 2 Parts List 5 3 5 3 Board Stackup and Layouts 5 4 5 3 References 5 6 Chapter 5 ...

Page 20: ...Schematic 5 2 5 1 Schematic Figure 5 1 Schematic of EVM Signal Path ...

Page 21: ... Header 3X2 8 3 J10 J14 J17 Header 2 POS 22 28 4020 Molex 9 2 L2 L1 Ferrite bead 50 Ω at 100 MHZ BLM31PG500SN1L Murata 10 1 P1 VCC MODEL 3267 Pomona 11 1 P2 GND MODEL 3267 Pomona 12 4 R1 R2 R13 R14 150 Ω 1 16W 5 0402 ERJ 2GEJ151X Panasonic 13 4 R3 R4 R7 R8 NI 4990 ERJ 2RKF4991X Panasonic 14 4 R5 R6 R9 R10 60 4 kΩ ERJ 2RKF6042X Panasonic 15 2 R11 R12 49 9 Ω 1 16W 1 0402 ERJ 2RKF49R9X Panasonic 16 1...

Page 22: ...Schematic 5 4 5 3 Board Stack Up and Layer Patterns Figure 5 2 Top Layer Figure 5 3 PWR1 Layer ...

Page 23: ...Schematic 5 5 Schematic Parts List Board Stackup Board Layouts and References Figure 5 4 GND1 Layer Figure 5 5 Bottom Layer ...

Page 24: ...PECL LVDS and CML Texas Instruments application report Texas Instruments SCAA056 3 CDCM1804 1 3 LVPECL Clock Buffer and Additional LVCMOS Output and Programmable Divider data sheet Texas Instruments SCAS697 4 CDCP1803 data sheet Texas Instruments SCAS727 5 DC Coupling between LVPECL LVDS CML and HSTL Texas Instruments application report Texas Instruments SCAA062 ...

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