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6
ChronosGUI
6.1
Using Software-Enabled Automatic PLL Selection
ChronosGUI
After the setup wizard completes, start the GUI interface from the Start menu (Start
→
Texas
Instruments
→
Chronos Eval
→
TIChronosGUI.exe).
Connect the USB cable to the EVM. If Microsoft Windows prompts you for an appropriate driver, do not
use the automatic search option. Select a manual installation. When prompted for the driver location,
browse to the Chronos GUI file folder that was created during installation. (If the operating system does
not ask for a driver, no additional action is needed.)
Once the USB driver installation completes, the GUI software should connect properly and be ready for
use. A green light in the USB communication box indicates a good USB connection; a red light indicates a
faulty USB connection. If the connection is not established, attempt to re-install the drivers.
Figure 5
shows the Chronos GUI used to navigate the EVM software.
Figure 5. TI Chronos Software GUI
The software illustration
Figure 5
shows the on-chip PLL structure of the CDCE421. Through this screen,
the user can change the Input Frequency, PFD Charge Pump, Loop Filter, and Output Type. The other
features are selected by the software; user-selectable options are described in this section.
Step 1.
IC Block Configuration and Input Calculator.
Before programming the PLL, the specific EVM block that is being programmed must be selected in
the IC Block Config section of the GUI. For any block in the EVM being used, the first row of
calculations is useful when trying to investigate the input frequency to the CDCE421 needed to obtain
a desired output frequency. The input frequency is obtained by pressing the Calculate button.
Step 2.
Store Crystal Frequency.
If a crystal input is used for Block B of the EVM, the crystal frequency must be entered into the space
provided; click on the Device_EEPROM drop-down menu at the top of the software GUI. A menu item
labeled Save Block B–XTAL Freq to EEPROM appears; this menu item must be selected. The crystal
SCAU020 – March 2007
10.9MHz–1175MHz Low Phase Noise Clock Evaluation Board
9
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