CC1000
SWRS048A Page 42 of 55
PA_POW Register (0Bh)
REGISTER
NAME
Default
value
Active
Description
PA_POW[7:4] PA_HIGHPOWER[3:0] 0000
- Control of output power in high power array.
Should be 0000 in PD mode . See Table 11
page 32 for details.
PA_POW[3:0] PA_LOWPOWER[3:0] 1111
- Control of output power in low power array
Should be 0000 in PD mode. See Table 11
page 32 for details.
PLL Register (0Ch)
REGISTER
NAME
Default
value
Active
Description
PLL[7]
EXT_FILTER
0
-
1 : External loop filter
0 : Internal loop filter
1-to-0 transition samples F_COMP
comparator when BREAK_LOOP=1
(TEST3)
PLL[6:3] REFDIV[3:0]
0010
-
Reference
divider
0000 : Not allowed
0001 : Not allowed
0010 : Divide by 2
0011 : Divide by 3
…........
1111 : Divide by 15
PLL[2]
ALARM_DISABLE
0
h
0 : Alarm function enabled
1 : Alarm function disabled
PLL[1] ALARM_H -
-
Status
bit
for tuning voltage out of range
(too close to VDD)
PLL[0] ALARM_L -
-
Status
bit
for tuning voltage out of range
(too close to GND)
