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CC1000

SWRS048A Page 15 of 55

10. Microcontroller Interface

Used in a typical system,

CC1000

will

interface to a microcontroller. This
microcontroller must be able to:

•

Program

CC1000

into different modes

via the 3-wire serial configuration
interface (PDATA, PCLK and PALE).

•

Interface to the bi-directional

synchronous data signal interface
(DIO and DCLK).

•

Optionally the microcontroller can do

data encoding / decoding.

•

Optionally the microcontroller can

monitor the frequency lock status from
pin CHP_OUT (LOCK).

•

Optionally the microcontroller can

monitor the RSSI output for signal
strength acquisition.

10.1 Connecting the microcontroller

The microcontroller uses 3 output pins for
the configuration interface (PDATA, PCLK
and PALE). PDATA should be a bi-
directional pin for data read-back. A bi-
directional pin is used for data (DIO) to be
transmitted and data received. DCLK
providing the data timing should be
connected to a microcontroller input.
Optionally another pin can be used to
monitor the LOCK signal (available at the
CHP_OUT pin). This signal is logic level
high when the PLL is in lock. See

Also the RSSI signal can be connected to
the microcontroller if it has an analogue
ADC input.

The microcontroller pins connected to
PDATA and PCLK can be used for other
purposes when the configuration interface
is not used. PDATA and PCLK are high
impedance inputs as long as PALE is
high.

PALE has an internal pull-up resistor and
should be left open (tri-stated by the
microcontroller) or set to a high level
during power down mode in order to
prevent a trickle current flowing in the pull-
up. The pin state in power down mode is
summarized in Table 3.

Pin

Pin state

Note

PDATA

Input

Should be driven high or low

PCLK

Input

Should be driven high or low

PALE

Input with internal pull-
up resistor

Should be driven high or high-impedance to minimize
power consumption

DIO

Input

Should be driven high or low

DCLK High-impedance

output

Table 3. CC1000 pins in power-down mode

CC1000

PDATA
PCLK
PALE

DIO

CHP_OUT
(LOCK)

Micro-
controller

DCLK

(Optional)

RSSI/IF

(Optional)

ADC

Figure 6. Microcontroller interface

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14
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17
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Summary of Contents for CC1070RSQ

Page 1: ...grammed via a serial bus thus making CC1000 a very flexible and easy to use transceiver In a typical system CC1000 will be used together with a microcontroller and a few external passive components CC1000 is based on Chipcon s SmartRF technology in 0 35 µm CMOS Features True single chip UHF RF transceiver Very low current consumption Frequency range 300 1000 MHz Integrated bit synchroniser High se...

Page 2: ...guration Overview 12 8 Configuration Software 12 9 3 wire Serial Configuration Interface 13 Note The set up and hold times refer to 50 of VDD 14 10 Microcontroller Interface 15 10 1 Connecting the microcontroller 15 11 Signal interface 16 11 1 Manchester encoding and decoding 16 12 Bit synchroniser and data decision 19 13 Receiver sensitivity versus data rate and frequency separation 22 14 Frequen...

Page 3: ...stems 37 26 6 Frequency hopping spread spectrum systems 37 27 PCB Layout Recommendations 38 28 Antenna Considerations 38 L 7125 f 38 29 Configuration registers 39 30 Package Description TSSOP 28 48 31 Package Description UltraCSP 49 32 Plastic Tube Specification 51 33 Waffle Pack Specification 51 34 Carrier Tape and Reel Specification 51 35 Ordering Information 52 36 General Information 52 36 1 Do...

Page 4: ...ld be used when handling the device in order to prevent permanent damage 2 Operating Conditions Parameter Min Typ Max Unit Condition Note RF Frequency Range 300 1000 MHz Programmable in steps of 250 Hz Operating ambient temperature range 40 85 C Supply voltage 2 1 3 0 3 6 V Note The same supply voltage should be used for digital DVDD and analogue AVDD power 3 Electrical Specifications Tc 25 C VDD ...

Page 5: ...a 64 kHz frequency separation BER 10 3 See Table 6 and Table 7 page 22 for typical sensitivity figures at other data rates System noise bandwidth 30 kHz 2 4 kBaud Manchester coded data Cascaded noise figure 433 868 MHz 12 13 dB Saturation 10 dBm 2 4 kBaud Manchester coded data BER 10 3 Input IP3 18 dBm From LNA to IF output Blocking 40 dBc At 1 MHz LO leakage 57 dBm Input impedance 88 j26 70 j26 5...

Page 6: ... 16 pF load 7 3728 MHz 16 pF load 16 MHz 16 pF load Output signal phase noise 85 dBc Hz At 100 kHz offset from carrier PLL lock time RX TX turn time 200 µs Up to 1 MHz frequency step PLL turn on time crystal oscillator on in power down mode 250 µs Crystal oscillator running Digital Inputs Outputs Logic 0 input voltage 0 0 3 VDD V Logic 1 input voltage 0 7 VDD VDD V Logic 0 output voltage 0 0 4 V O...

Page 7: ...ng 1 100 receive to power down ratio Current Consumption transmit mode 433 868 MHz P 0 01mW 20 dBm P 0 3 mW 5 dBm P 1 mW 0 dBm P 3 mW 5 dBm P 10 mW 10 dBm 5 3 8 6 8 9 13 8 10 4 16 5 14 8 25 4 26 7 NA mA mA mA mA mA The ouput power is delivered to a 50Ω load see also p 32 Current Consumption crystal osc Current Consumption crystal osc And bias Current Consumption crystal osc bias and synthesiser RX...

Page 8: ...ystal pin 1 or external clock input 19 B4 AGND Ground A Ground connection 0 V for analog modules guard 20 C3 DGND Ground D Ground connection 0 V for digital modules substrate 21 C4 DVDD Power D Power supply 3 V for digital modules 22 D4 DGND Ground D Ground connection 0 V for digital modules 23 E4 DIO Digital input output Data input output Data input in transmit mode Data output in receive mode 24...

Page 9: ...d oscillator VCO output signal is fed directly to the power amplifier PA The RF output is frequency shift keyed FSK by the digital bit stream fed to the pin DIO The internal T R switch circuitry makes the antenna interface and matching very easy The frequency synthesiser generates the local oscillator signal which is fed to the MIXER in receive mode and to the PA in transmit mode The frequency syn...

Page 10: ...ly integrated except for the inductor L101 Component values for the matching network and VCO inductor are easily calculated using the SmartRF Studio software 6 3 Additional filtering Additional external components e g RF LC or SAW filter may be used in order to improve the performance in specific applications See also Optional LC filter p 36 for further information 6 4 Power supply decoupling Powe...

Page 11: ... Not used C42 4 7 pF 5 C0G 0402 4 7 pF 5 C0G 0402 6 8 pF 5 C0G 0402 6 8 pF 5 C0G 0402 C171 18 pF 5 C0G 0402 18 pF 5 C0G 0402 18 pF 5 C0G 0402 18 pF 5 C0G 0402 C181 18 pF 5 C0G 0402 18 pF 5 C0G 0402 18 pF 5 C0G 0402 18 pF 5 C0G 0402 L32 39 nH 5 0402 Ceramic multilayer 68 nH 5 0402 Ceramic multilayer 120 nH 5 0402 Ceramic multilayer 120 nH 5 0402 Ceramic multilayer L41 22 nH 5 0402 Ceramic multilaye...

Page 12: ...ormat NRZ Manchester coded or UART interface Synthesiser lock indicator mode Optional RSSI or external IF 8 Configuration Software Chipcon provides users of CC1000 with a software program SmartRF Studio Windows interface that generates all necessary CC1000 configuration data based on the user s selections of various parameters These hexadecimal numbers will then be the necessary input to the micro...

Page 13: ...e PALE Program Address Latch Enable must be kept low The 8 data bits are then transferred D7 0 See Figure 4 The timing for the programming is also shown in Figure 4 with reference to Table 2 The clocking of the data on PDATA is done on the negative edge of PCLK When the last bit D0 of the 8 data bits has been loaded the data word is loaded in the internal configuration register The configuration d...

Page 14: ... hold time THA 10 ns The minimum time PALE must be held low after the positive edge of PCLK PDATA setup time TSD 10 ns The minimum time data on PDATA must be ready before the negative edge of PCLK PDATA hold time THD 10 ns The minimum time data must be held at PDATA after the negative edge of PCLK Rise time Trise 100 ns The maximum rise time for PCLK and PALE Fall time Tfall 100 ns The maximum fal...

Page 15: ...another pin can be used to monitor the LOCK signal available at the CHP_OUT pin This signal is logic level high when the PLL is in lock See Figure 6 Also the RSSI signal can be connected to the microcontroller if it has an analogue ADC input The microcontroller pins connected to PDATA and PCLK can be used for other purposes when the configuration interface is not used PDATA and PCLK are high imped...

Page 16: ...Baud due to the Manchester encoding For 38 4 and 76 8 kBaud a crystal frequency of 14 7456 MHz must be used In receive mode CC1000 does the synchronisation and provides received data clock at DCLK and data at DIO CC1000 does the decoding and NRZ data is presented at DIO The data should be clocked into the interfacing circuit at the rising edge of DCLK See Figure 8 Transparent Asynchronous UART mod...

Page 17: ...lock provided by CC1000 Demodulated signal NRZ internal in CC1000 Data provided by CC1000 Receiver side RF DCLK DIO DIO DCLK RF Clock provided by CC1000 FSK modulating signal Manchester encoded internal in CC1000 Data provided by microcontroller NRZ Transmitter side Clock provided by CC1000 Demodulated signal Manchester encoded internal in CC1000 Data provided by CC1000 NRZ Receiver side RF DCLK D...

Page 18: ...DIO is not used in receive mode Used only as data input in transmit mode Demodulated signal internal in CC1000 Data output provided by CC1000 Connect to UART RXD Receiver side RF DIO DCLK DIO DCLK RF DCLK is not used in transmit mode Used as data output in receive mode FSK modulating signal internal in CC1000 Data provided by UART TXD Transmitter side DIO is not used in receive mode Used only as d...

Page 19: ...iving a 011001100110 chip pattern This is necessary for the bit synchronizer to synchronize correctly The averaging filter must be locked before any NRZ data can be received If the averaging filter is locked MODEM1 LOCK_AVG_MODE 1 the acquired value will be kept also after Power Down or Transmit mode After a modem reset MODEM1 MODEM_RESET_N or a main reset using any of the standard reset sources t...

Page 20: ...hen MODEM1 LOCK_AVG_IN is set to 1 X Do not care The timer for the automatic lock is started when RX mode is set in the RFMAIN register Also please note that in addition to the number of bits required to lock the filter you need to add the number of bits needed for the preamble detector See the next section for more information Table 4 Minimum preamble bits for locking the averaging filter NRZ and...

Page 21: ...eraging filter Preamble NRZ data Data package to be received RX Noise PD Averaging filter free running Manually locked after preamble is detected Noise Averaging filter locked Preamble NRZ data Data package to be received RX Noise PD Averaging filter free running Manually locked after preamble is detected Noise Averaging filter locked Figure 13 Manual locking of the averaging filter Preamble Manch...

Page 22: ... mA 11 8 mA Table 6 Receiver sensitivity as a function of data rate at 433 and 868 MHz BER 10 3 frequency separation 64 kHz normal current settings 433 MHz 868 MHz Data rate kBaud Separation kHz NRZ mode Manchester mode UART mode NRZ mode Manchester mode UART mode 0 6 20 109 111 109 106 108 106 1 2 20 108 110 108 104 106 104 2 4 20 106 108 106 103 105 103 4 8 20 104 106 104 101 103 101 9 6 20 103 ...

Page 23: ..._1B FREQ_0B for the A and B word respectively The frequency word FREQ can be calculated from 16384 8192 TXDATA FSEP FREQ f f ref VCO where TXDATA is 0 or 1 in transmit mode depending on the data bit to be transmitted on DIO In receive mode TXDATA is always 0 The reference frequency fref is the crystal oscillator clock divided by PLL REFDIV a number between 2 and 14 that should be chosen such that ...

Page 24: ...V decimal Frequency word RX mode FREQ decimal Frequency word RX mode FREQ hex 315 315 037200 3 6864 High side 3 4194304 400000 7 3728 6 4194304 400000 11 0592 9 4194304 400000 14 7456 12 4194304 400000 433 3 433 302000 3 6864 Low side 3 5775168 580000 7 3728 6 5775168 580000 11 0592 9 5775168 580000 14 7456 12 5775168 580000 433 9 433 916400 3 6864 Low side 3 5775360 582000 7 3728 6 5775360 582000...

Page 25: ...y MHz Calibration time ms 2 4 14 2 0 17 1 5 23 1 0 34 The CAL_COMPLETE bit can also be monitored at the CHP_OUT LOCK pin configured by LOCK_SELECT 3 0 and used as an interrupt input to the microcontroller The CAL_START bit must be set to 0 by the microcontroller after the calibration is done There are separate calibration values for the two frequency registers If the two frequencies A and B differ...

Page 26: ... to prevent spurious emission Calibration time depend on the reference frequency see text Write CAL CAL_START 0 End of calibration Wait for maximum 34 ms or Read CAL and wait until CAL_COMPLETE 1 Start single calibration RX frequency register A is calibrated first Write MAIN RXTX 0 F_REG 0 RX_PD 0 TX_PD 1 FS_PD 0 CORE_PD 0 BIAS_PD 0 RESET_N 1 Write FREQ_A FREQ_B If DR 9 6kBd then write TEST4 L2KIO...

Page 27: ...ate CURRENT and PLL for RX mode Calibration time depend on the reference frequency see text Write CAL CAL_START 0 End of calibration Wait for maximum 34 ms or Read CAL and wait until CAL_COMPLETE 1 Start dual calibration Either frequency register A or B is selected Write MAIN RXTX 0 F_REG 0 RX_PD 0 TX_PD 1 FS_PD 0 CORE_PD 0 BIAS_PD 0 RESET_N 1 Write FREQ_A FREQ_B If DR 38kBd then write TEST4 L2KIO...

Page 28: ...nsumption and sensitivity are typical figures at 2 4 kBaud Manchester encoded data BER 10 3 Table 10 Receiver sensitivity as function of current consumption 19 Power management CC1000 offers great flexibility for power management in order to meet strict power consumption requirements in battery operated applications Power Down mode is controlled through the MAIN register There are separate bits to...

Page 29: ... Time to wait depends on the crystal frequency and the load capacitance MAIN RX_PD 1 TX_PD 1 FS_PD 1 CORE_PD 1 BIAS_PD 1 PA_POW 00h Power Down Power Off Power turned on Initialise and reset CC1000 MAIN RXTX 0 F_REG 0 RX_PD 1 TX_PD 1 FS_PD 1 CORE_PD 0 BIAS_PD 1 RESET_N 0 Program all registers except MAIN Frequency register A is used for RX mode register B for TX Calibrate VCO and PLL Calibration is...

Page 30: ...0 CURRENT RX current PLL RX pll Wait 250 µs RX or TX Power Down Time to wait depends on the crystal frequency and the load capacitance RX mode Turn off RX MAIN RX_PD 1 FS_PD 1 CORE_PD 1 BIAS_PD 1 Power Down Turn on TX PA_POW 00h MAIN RXTX 1 F_REG 1 TX_PD 0 FS_PD 0 CURRENT TX current PLL RX pll Wait 250 µs TX mode Turn off TX MAIN TX_PD 1 FS_PD 1 CORE_PD 1 BIAS_PD 1 PA_POW 00h Power Down PA_POW Out...

Page 31: ...mponent values for various frequencies are given in Table 1 Component values for other frequencies can be found using the configuration software Figure 20 Input output matching network RF_IN RF_OUT TO ANTENNA CC1000 L41 C41 C42 AVDD 3V L32 C31 RF_IN RF_OUT TO ANTENNA CC1000 L41 C41 C42 AVDD 3V L32 C31 RF_IN RF_OUT TO ANTENNA CC1000 L41 C41 C42 AVDD 3V L32 C31 RF_IN RF_OUT TO ANTENNA CC1000 L41 C41...

Page 32: ...onsumption typ mA PA_POW hex Current consumption typ mA 20 01 6 9 02 8 6 19 01 6 9 02 8 8 18 02 7 1 03 9 0 17 02 7 1 03 9 0 16 02 7 1 04 9 1 15 03 7 4 05 9 3 14 03 7 4 05 9 3 13 03 7 4 06 9 5 12 04 7 6 07 9 7 11 04 7 6 08 9 9 10 05 7 9 09 10 1 9 05 7 9 0B 10 4 8 06 8 2 0C 10 6 7 07 8 4 0D 10 8 6 08 8 7 0F 11 1 5 09 8 9 40 13 8 4 0A 9 6 50 14 5 3 0B 9 4 50 14 5 2 0C 9 7 60 15 1 1 0E 10 2 70 15 8 0 ...

Page 33: ...erminating resistor giving approximately 50 dB V This RSSI voltage can be measured by an A D converter Note that a higher voltage means a lower input signal The RSSI measures the power referred to the RF_IN pin The input power can be calculated using the following equations P 51 3 VRSSI 49 2 dBm at 433 MHz P 50 0 VRSSI 45 5 dBm at 868 MHz The external network for RSSI operation is shown in Figure ...

Page 34: ... then built with CC1000 a 10 7 MHz ceramic filter and an external 10 7 MHz demodulator The external network for IF output operation is shown in Figure 23 R281 470 Ω C281 3 3nF The external network provides 330 Ω source impedance for the 10 7 MHz ceramic filter RSSI IF CC1000 R281 C281 To 10 7MHz filter and demodulator RSSI IF CC1000 R281 C281 To 10 7MHz filter and demodulator Figure 23 IF output c...

Page 35: ...ate the new crystal frequency DR DR f f new xtal new xtal _ Using the internal crystal oscillator the crystal must be connected between XOSC_Q1 and XOSC_Q2 The oscillator is designed for parallel mode operation of the crystal In addition loading capacitors C171 and C181 for the crystal are required The loading capacitor values depend on the total load capacitance CL specified for the crystal The t...

Page 36: ...ceiver selectivity The filter topology is shown in Figure 25 Component values are given in Table 13 The filter is designed for 50 Ω terminations The component values may have to be tuned to compensate for layout parasitics L71 C71 C72 L71 C71 C72 Figure 25 LC filter Item 315 MHz 433 MHz 868 MHz 915 MHz C71 30 pF 20 pF 10 pF 10 pF C72 30 pF 20 pF 10 pF 10 pF L71 15 nH 12 nH 5 6 nH 4 7 nH Table 13 L...

Page 37: ...sensor is included in the system Even initial adjustment can be done using the frequency programmability This eliminates the need for an expensive TCXO and trimming in some applications In less demanding applications a crystal with low temperature drift and low ageing could be used without further compensation A trimmer capacitor in the crystal oscillator circuit in parallel with C171 could be use...

Page 38: ...ith the power supply ground A development kit with a fully assembled PCB is available and can be used as a guideline for layout 28 Antenna Considerations CC1000 can be used together with various types of antennas The most common antennas for short range communication are monopole helical and loop antennas Monopole antennas are resonant antennas with a length corresponding to one quarter of the ele...

Page 39: ...NT Current Consumption Control Register 0Ah FRONT_END Front End Control Register 0Bh PA_POW PA Output Power Control Register 0Ch PLL PLL Control Register 0Dh LOCK LOCK Status Register and signal select to CHP_OUT LOCK pin 0Eh CAL VCO Calibration Control and Status Register 0Fh MODEM2 Modem Control Register 2 10h MODEM1 Modem Control Register 1 11h MODEM0 Modem Control Register 0 12h MATCH Match Ca...

Page 40: ... Description FREQ_2A 7 0 FREQ_A 23 16 01110101 8 MSB of frequency control word A FREQ_1A Register 02h REGISTER NAME Default value Active Description FREQ_1A 7 0 FREQ_A 15 8 10100000 Bit 15 to 8 of frequency control word A FREQ_0A Register 03h REGISTER NAME Default value Active Description FREQ_0A 7 0 FREQ_A 7 0 11001011 8 LSB of frequency control word A FREQ_2B Register 04h REGISTER NAME Default v...

Page 41: ...0 Control of current in VCO buffer for PA 00 1mA use for RX 01 2mA use for TX f 500 MHz 10 3mA 11 4mA use for TX f 500 MHz FRONT_END Register 0Ah REGISTER NAME Default value Active Description FRONT_END 7 6 00 Not used FRONT_END 5 BUF_CURRENT 0 Control of current in the LNA_FOLLOWER 0 520uA use for f 500 MHz 1 690uA use for f 500 MHz BUF_CURRENT can be reduced to save current in RX mode See Table ...

Page 42: ...or details PLL Register 0Ch REGISTER NAME Default value Active Description PLL 7 EXT_FILTER 0 1 External loop filter 0 Internal loop filter 1 to 0 transition samples F_COMP comparator when BREAK_LOOP 1 TEST3 PLL 6 3 REFDIV 3 0 0010 Reference divider 0000 Not allowed 0001 Not allowed 0010 Divide by 2 0011 Divide by 3 1111 Divide by 15 PLL 2 ALARM_DISABLE 0 h 0 Alarm function enabled 1 Alarm functio...

Page 43: ...eset Lock Threshold 15 Corresponds to a worst case accuracy of 2 8 LOCK 2 PLL_LOCK_ LENGTH 0 0 Normal PLL lock window 1 Not used LOCK 1 LOCK_INSTANT Status bit from Lock Detector LOCK 0 LOCK_CONTINUOUS Status bit from Lock Detector CAL Register 0Eh REGISTER NAME Default value Active Description CAL 7 CAL_START 0 1 Calibration started 0 Calibration inactive CAL_START must be set to 0 after calibrat...

Page 44: ... Flag is set 001 Violation Flag is set for Manchester Value 1 010 Violation Flag is set for Manchester Value 2 011 Violation Flag is set for Manchester Value 3 100 Violation Flag is set for Manchester Value 4 101 Violation Flag is set for Manchester Value 5 110 Violation Flag is set for Manchester Value 6 111 Violation Flag is set for Manchester Value 7 MODEM1 4 LOCK_AVG_IN 0 H Lock control bit of...

Page 45: ...Also used for 76 8 kBaud 14 7456MHz 01 6MHz 8MHz crystal 7 3728MHz recommended Also used for 38 4 kBaud 14 7456MHz 10 9MHz 12MHz crystal 11 0592 MHz recommended 11 12MHz 16MHz crystal 14 7456MHz recommended MATCH Register 12h REGISTER NAME Default value Active Description MATCH 7 4 RX_MATCH 3 0 0000 Selects matching capacitor array value for RX step size is 0 4 pF 0001 Use for RF frequency 500 MHz...

Page 46: ...ult value Active Description TEST6 7 LOOPFILTER_TP1 0 1 Select testpoint 1 to CHP_OUT 0 CHP_OUT tied to GND TEST6 6 LOOPFILTER_TP2 0 1 Select testpoint 2 to CHP_OUT 0 CHP_OUT tied to GND TEST6 5 CHP_OVERRIDE 0 1 use CHP_CO 4 0 value 0 use calibrated value TEST6 4 0 CHP_CO 4 0 10000 Charge_Pump Current DAC override value TEST5 Register for test only 41h REGISTER NAME Default value Active Descriptio...

Page 47: ...only 44h REGISTER NAME Default value Active Description TEST2 7 5 Not used TEST2 4 0 CHP_CURRENT 4 0 Status vector defining applied CHP_CURRENT value TEST1 Register for test only 45h REGISTER NAME Default value Active Description TEST1 7 4 Not used TEST1 3 0 CAL_DAC 3 0 Status vector defining applied Calibration DAC value TEST0 Register for test only 46h REGISTER NAME Default value Active Descript...

Page 48: ...ge Description TSSOP 28 Note The figure is an illustration only Thin Shrink Small Outline Package TSSOP D E1 E A A1 e B L Copl α TSSOP 28 Min Max 9 60 9 80 4 30 4 50 6 40 1 20 0 05 0 15 0 65 0 19 0 30 0 45 0 75 0 10 0 8 All dimensions in mm ...

Page 49: ...traCSP Top view 250um 10um 500um 10um 500um 10um A1 B1 C1 D1 E1 F1 G1 A2 B2 C2 D2 E2 F2 G2 A3 B3 C3 D3 E3 F3 G3 A4 B4 C4 D4 E4 F4 G4 292um 20um 392um 20um 4034um 20um 2339um 20um 535um 20um 417um 20um Bump pitch is 500um centre to centre in both directions ...

Page 50: ...unting pads Solder bumps Pb free Before assembly on PCB After assembly on PCB Die thickness A Bump height before assembly h1 Bump height after assembly h2 Total height before assembly Total height after assembly 432um 200um 20um 140um tbd um 632um 20um 572um tbd um Table 14 Height budget ...

Page 51: ...ation Package Waffle Pack Width Waffle Pack Length Waffle Pack Length Units per Waffle Pack UltraCSP 50 8 mm 50 8 mm 3 96 mm 117 34 Carrier Tape and Reel Specification Carrier tape and reel is in accordance with EIA Specification 481 Tape and Reel Specification Package Tape Width Component Pitch Hole Pitch Reel Diameter Units per Reel TSSOP 28 16 mm 8 mm 4 mm 13 2500 UltraCSP 12 mm 8 mm 4 mm 4 mm ...

Page 52: ...CC1000 UltraCSP updated to 255 C Added waffle pack specification Updated ordering information with TI part numbers Updated address information Updated header and footer Updated Important Notice Removed Chipcon specific Disclaimer Trademarks and Life Support Policy sections SWRS048 2 3 August 2005 UltraCSP package included Minor corrections and editorial changes 2 2 April 2004 Shaping feature remov...

Page 53: ...55 Data Sheet Identification Product Status Definition Obsolete Not In Production This data sheet contains specifications on a product that has been discontinued by Chipcon The data sheet is printed for reference information only ...

Page 54: ... Fax 1 972 927 6377 Internet Email support ti com sc pic americas htm Europe Middle East and Africa Phone Belgium English 32 0 27 45 54 32 Finland English 358 0 9 25173948 France 33 0 1 30 70 11 64 Germany 49 0 8161 80 33 11 Israel English 180 949 0107 Italy 800 79 11 37 Netherlands English 31 0 546 87 95 45 Russia 7 0 95 363 4824 Spain 34 902 35 40 28 Sweden English 46 0 8587 555 22 United Kingdo...

Page 55: ... India 91 80 51381665 Toll Indonesia 001 803 8861 1006 Korea 080 551 2804 Malaysia 1 800 80 3973 New Zealand 0800 446 934 Philippines 1 800 765 7404 Singapore 800 886 1028 Taiwan 0800 006800 Thailand 001 800 886 0010 Fax 886 2 2378 6808 Email tiasia ti com or ti china ti com Internet support ti com sc pic asia htm Copyright 2007 Texas Instruments Incorporated ...

Page 56: ...vice Package Type Package Drawing Pins SPQ Reel Diameter mm Reel Width W1 mm A0 mm B0 mm K0 mm P1 mm W mm Pin1 Quadrant CC1000PWR TSSOP PW 28 2500 330 0 16 4 6 8 10 2 1 6 8 0 16 0 Q1 PACKAGE MATERIALS INFORMATION www ti com 5 Jan 2022 Pack Materials Page 1 ...

Page 57: ...nsions are nominal Device Package Type Package Drawing Pins SPQ Length mm Width mm Height mm CC1000PWR TSSOP PW 28 2500 378 0 70 0 346 0 PACKAGE MATERIALS INFORMATION www ti com 5 Jan 2022 Pack Materials Page 2 ...

Page 58: ...minal Device Package Name Package Type Pins SPQ L mm W mm T µm B mm CC1000 RTB1 PW TSSOP 28 50 509 6 8 2000 4 06 CC1000PW PW TSSOP 28 50 509 6 8 2000 4 06 PACKAGE MATERIALS INFORMATION www ti com 5 Jan 2022 Pack Materials Page 3 ...

Page 59: ...o change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you will fully indemn...

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