Hardware
Table 6. J2 -Thermistor Connector Pin
Assignments (continued)
Pin Number
Pin Function
15
AUX6 (Thermistor 7)
16
AUX7 (Thermistor 8)
NOTE:
Pins number assignments on the J2 - Thermistor connector are such that, when looking into
the mouth of the connector, the bottom of row of the connector is numbered 1–8 from right to
left, and the top row of the connector is numbered from 9–16 from right to left. Pin 1 on the
connector has a square pad on the bottom of the PCB. Additionally, pins 1, 8, 9, and 16 are
labeled with silk-screened numbers.
The mating connector from Molex Connector Corporation is part number 43025-1600.
Digikey Corporation: WM2490-ND.
The crimp pin for this mating connector from Molex Connector Corporation is part number 46235-5001 (or
46235-5002).
Digikey Corporation: WM2258TR-ND or WM2258CT-ND. (An alternate base number for different plating
option is WM2259.)
The part number for the crimper to create custom cables using the above parts from Molex Connector
Corporation is: 63819-2900.
Digikey Corporation: WM4747-ND.
5.2.5
P1 - GPIO Header
The bq76PL455A-Q1 implements six General Purpose Input/Output (GPIO) signals. The bq76PL455EVM
provides access to these GPIO pins (in addition to the VIO supply and DGND) at the 14-pin 7x2
unshrouded P1 - GPIO header. Configure the GPIO pins as input or output by writing to specific
configuration registers in the bq76PL455A-Q1. Additionally, program configuration registers to choose
internal pull-up or pull-down resistors for any of the GPIO pins. Digital input signals are read by reading
the General Purpose Input register, and digital output values are set by writing to the General Purpose
Output register in the bq76PL455A-Q1. These registers can be written and read using the
Register View
window from the GUI (see
). The bq76PL455A-Q1 data sheet (
) provides additional
details.
When configured as inputs, the GPI can also be selectively programmed to generate fault signals when
changing state either from digital high to low or from digital low to high. This configuration is done on the
Fault Mask
tab in the GUI, and triggered faults are viewed on the Faults tab.
shows pin assignments for the P1 - GPIO header.
Table 7. P1 - GPIO Header Pin Assignments
Pin Number
Pin Function
1
GPIO0
2
Ground (DGND)
3
GPIO1
4
Ground (DGND)
5
GPIO2
6
Ground (DGND)
7
GPIO3
8
Ground (DGND)
9
GPIO4
10
Ground (DGND)
15
SLUUBA7A – April 2015 – Revised July 2015
bq76PL455EVM and GUI User Guide
Copyright © 2015, Texas Instruments Incorporated
