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9.5.1.20 LDOCTRL Register (Address = 0x1D) [reset = 0xB0]

LDOCTRL is shown in

Figure 9-35

and described in

Table 9-29

Return to

Summary Table

Figure 9-35. LDOCTRL Register

EN_LS_LDO

VLDO_4:0

LDO_SWITCH_

CONFG

RESERVED

R/W-1b1

R/W-5b01100

R/W-1b0

Table 9-29. LDOCTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

EN_LS_LDO

R/W

1b1

LS/LDO Enable
1b0 = Disable LS/LDO
1b1 = Enable LS/LDO

6-2

VLDO_4:0

R/W

5b01100

LDO output voltage setting (1.8 V default)
LDO Voltage = 600 mV + VLDO Code x 100 mV

LDO_SWITCH_CONFG

R/W

1b0

LDO / Load Switch Configuration Select
1b0 = LDO
1b1 = Load Switch

RESERVED

R/W

1b0

Reserved

BQ25157

SLUSEC5 – DECEMBER 2020

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BQ25157

Summary of Contents for BQ25157

Page 1: ...s earbuds and hearing aids Smart watches and smart trackers Wearable fitness and activity monitors Blood glucose monitors 3 Description The BQ25157 is a highly integrated battery charge management IC...

Page 2: ...Register Map 39 10 Application and Implementation 94 10 1 Application Information 94 10 2 Typical Application 94 11 Power Supply Recommendations 100 12 Layout 101 12 1 Layout Guidelines 101 12 2 Layo...

Page 3: ...temperature using a thermistor connected to the TS pin as well as external system signals through the ADCIN pin The low quiescent current during operation and shutdown enables maximum battery life The...

Page 4: ...rent Ljmit IILIM 100 mA 500 mA 100 mA VIN DPM Enabled 4 5 V Disabled 4 6 V Enabled 4 2 V PMID Passthrough Regulated 4 5V Default Passthrough IMAX Enabled Disabled Disabled Ship Mode Wake Timer 2 secon...

Page 5: ...ging when VIN is valid Drive CE high to disable charge when VIN is present CE is pulled low internally with 900 k resistor CE has no effect when VIN is not present SCL E3 I O I2C Interface Clock Conne...

Page 6: ...s than VOVP PG is high impedance when the input power is not within specified limits Connect PG to the desired logic voltage rail using a 1 k to 100 k resistor or use with an LED for visual indication...

Page 7: ...101 all pins 2 500 1 JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process 2 JEDEC document JEP157 states that 250 V CDM allows safe manufacturing w...

Page 8: ...nabled 1 7 3 5 A IBAT_ACTI VE Battery Quiescent Current in Active Mode 0 C TJ 85 C VIN 0V VBAT 3 6V LDO Disabled 18 25 A 0 C TJ 85 C VIN 0V VBAT 3 6V LDO Enabled 21 27 A POWER PATH MANAGEMENT AND INPU...

Page 9: ...4 2V VRCH 140mV setting 140 mV VBAT falling VBATREG 4 2V VRCH 200mV setting 200 mV RPMID_PD PMID pull down resistance VPMID 3 6V 25 VDD VDD VDD LDO output voltage VBAT 3 6V VIN 0V 0 ILOAD_VDD 10mA 1...

Page 10: ...81 6 A PROTECTION VUVLO IN active threshold voltage VIN rising 3 4 V VIN falling 3 25 V VBATUVLO Battery undervoltage Lockout Threshold Voltage Programmable range 150 mV Hysteresis 2 4 3 V Accuracy 3...

Page 11: ...load to 90 VLDO 500 s tOFF_LDO Turn OFF time 100mA load to 10 VLDO 30 s tPMID_LDO _DELAY Delay between PMID and LDO enable during power up Startup 20 ms PUSHBUTTON TIMERS MR tWAKE1 WAKE1 Timer Time fr...

Page 12: ...ms tRETRY_SC Retry window for PMID or BAT short circuit recovery 2 s tDGL_SHT DWN Deglitch time Thermal shutdown TJ rising above TSHUTDOWN 10 s I2C INTERFACE tWATCHDO G I2C interface reset timer for h...

Page 13: ...2 7 V ICHARGE_RANGE 0 Figure 8 3 Pre Charge Current Accuracy vs IPRECHARGE setting ICHARGE_RANGE 0 IPRECHARGE A Error 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 1 2 1 0 8 0 6 0 4 0 2 0 0 2 0 4 0...

Page 14: ...02 1 204 1 206 1 208 1 21 D004 TJ 40C TJ 25C TJ 85C VBAT 4 4 V ILOAD 150 mA Figure 8 9 LDO Line Regulation VLDO 1 2 V VINLS V V LDO V 2 2 2 4 2 6 2 8 3 3 2 3 4 3 6 3 8 4 4 2 4 4 1 79 1 792 1 794 1 796...

Page 15: ...ush button controller allows the user to reset the system without any intervention from the host and wake up the device from Ship Mode 9 2 Functional Block Diagram LDO and BAT FET Control Device Contr...

Page 16: ...e the charge current constant current loop CC constant voltage loop CV input current limit VDPPM and VINDPM During the charging process all loops are enabled and the one that is dominant takes control...

Page 17: ...Flow Diagram When a valid input source is connected VIN VUVLO and VBAT VSLP VIN VOVP the state of the CE pin determines whether a charge cycle is initiated When the CE input is high and a valid input...

Page 18: ...oops that control charging when VBAT VLOWV the Constant Current CC and Constant Voltage CV loops When the CC loop is dominant typically when VBAT VBATREG 50 mV the battery is charged at the maximum ch...

Page 19: ...p of the supply voltage The VINDPM function is disabled by default and may be enabled through I2C command The VIN_DPM threshold is programmable through the I2C register from 4 2 V to 4 9 V in 100 mV s...

Page 20: ...d I2C watchdog timer that monitors the host through the I2C interface The watchdog timer is enabled by default and may be disabled by the host through I2C Once the watchdog timer is enabled the watchd...

Page 21: ...prevent stress on the device if a sudden short condition happens before allowing a softstart on the PMID output 9 3 3 ADC The device uses a 16 bit ADC to report information on the input voltage input...

Page 22: ...urrent setting Note that if the device is in pre charge or in the TS COLD region ICHARGE will be the current set by the IPRECHRG and TS_ICHRG bits respectively 9 3 3 4 ADC Programmable Comparators The...

Page 23: ..._LDOCODE 100 mV up to 3 7 V All higher codes will set the output to 3 7 V Table 9 3 LDO Mode Control I2C EN_LS_LDO LS_CONFIG LS LDO OUTPUT 0 0 Pulldown 0 1 Pulldown 1 0 LDO 1 1 Load Switch The current...

Page 24: ...s The timing for the short and long button press duration is programmable through I2C for added flexibility and allow system designers to customize the end user experience of a specific application No...

Page 25: ...ress Functions The BQ25157 device may be configured to perform a system hardware reset Power Cycle Autowake go into Ship Mode or simply do nothing after a long button press for example when the MR pin...

Page 26: ...he whole duration of the button press This flexibility allows the host to abort any reset or power shutdown to the system by overriding a long button press command A HW reset may also be started by se...

Page 27: ...action after VIN detected No HW Reset since function was not re enabled after boot up No HW Reset since I2C transaction occurred within 14s window of VIN detection Figure 9 7 14 Second Watchdog for HW...

Page 28: ...enabled N A VIN powered unless supplement mode condition is met THERMREG_AC TIVE Set when Thermal Charge Current Foldback Thermal Regulation loop is active Rising Edge Enabled Reduced charge current D...

Page 29: ...programmed condition Rising Edge N A N A N A N A TS_OPEN_FLA G Set when VTS VTS_OPEN Rising Edge Charging is paused until condition disappears Paused N A N A WD_FAULT_FLA G Set when I2C watchdog time...

Page 30: ...the pin is being sampled for about 25ms in 225ms intervals when VIN is present Note that the TS biasing cannot be disabled when VIN is present The part can be configured to meet JEITA requirements or...

Page 31: ...ough I2C based on the supported NTC type BQ25157 TS VDD NTC RPARALLEL RPARALLEL RNTC 25C ADC TS measurement control TS IBIAS Figure 9 8 TS Bias Functional Diagram The BQ25157 supports by default the f...

Page 32: ...most functions to be programmed to new values depending on the instantaneous application requirements Register contents remain intact as long as VBAT or VIN voltages remains above their respective UV...

Page 33: ...see Figure 9 9 This releases the bus and stops the communication link with the addressed slave All I2C compatible devices must recognize the stop condition Upon the receipt of a stop condition all de...

Page 34: ...Condition Generate ACKNOWLEDGE Signal Acknowledgement Signal From Slave MSB Address R W ACK S or Sr Sr or P P Sr ACK Figure 9 12 Bus Protocol BQ25157 SLUSEC5 DECEMBER 2020 www ti com 34 Submit Documen...

Page 35: ...and BAT FET until VIN VUVLO or the MR button is depressed for tWAKE1 and released Ship mode can be entered regardless of the state of CE The device will also enter Ship Mode upon battery insertion wh...

Page 36: ...o LP Mode tuning off all clocks Note that if a HW reset has occurred while LP is low MR must remain low until the power cycle has completed PMID and LDO enable to allow completion of the power up sequ...

Page 37: ...device to check the MR state and if MR is high VDD will immediately be disabled and the device will enter Ship Mode If MR is low the device will start the WAKE timer and power up PMID and other rails...

Page 38: ...MODE MR Deglitch Delay tWAKE2 Figure 9 15 BQ25157 Wake Up Upon Battery Insertion BQ25157 SLUSEC5 DECEMBER 2020 www ti com 38 Submit Document Feedback Copyright 2020 Texas Instruments Incorporated Prod...

Page 39: ...Current Control Go 0x16 BUVLO Battery UVLO and Current Limit Control Go 0x17 CHARGERCTRL0 Charger Control 0 Go 0x18 CHARGERCTRL1 Charger Control 1 Go 0x19 ILIMCTRL Input Corrent Limit Control Go 0x1D...

Page 40: ...ADC_READ_EN ADC Channel Enable Go 0x61 TS_FASTCHGCTRL TS Charge Control Go 0x62 TS_COLD TS Cold Threshold Go 0x63 TS_COOL TS Cool Threshold Go 0x64 TS_WARM TS Warm Threshold Go 0x65 TS_HOT TS Hot Thre...

Page 41: ...t Voltage Charging Mode Taper Mode Status 1b0 Not Active 1b1 Active 5 CHARGE_DONE_STAT R X Charge Done Status 1b0 Not Active 1b1 Active 4 IINLIM_ACTIVE_STAT R X Input Current Limit Status 1b0 Not Acti...

Page 42: ...Over Current Protection Status 1b0 Not Active 1b1 Active 4 BAT_UVLO_FAULT_STAT R X Battery voltage below BATUVLO Level Status 1b0 VBAT VBATUVLO 1b1 VBAT VBATUVLO 3 TS_COLD_STAT R X TS Cold Status VTS...

Page 43: ...E bit 1b1 Selected ADC measurement meets condition set by 1_ADCALARM_ABOVE bit 5 COMP2_ALARM_STAT R X COMP2 Status 1b0 Selected ADC measurement does not meet condition set by 2_ADCALARM_ABOVE bit 1b1...

Page 44: ...LAG RC 1b0 Charge Done Flag 1b0 Charge Done Termination not detected 1b1 Charge Done Termination detected 4 IINLIM_ACTIVE_FLAG RC 1b0 Input Current Limit Flag 1b0 Input Current Limit not detected 1b1...

Page 45: ...lag 1b0 No Battery Over Current condition detected 1b1 Battery Over Current condition detected 4 BAT_UVLO_FAULT_FLAG RC 1b0 Battery Under Voltage Flag 1b0 Battery below BATUVLO condition detected 1b1...

Page 46: ...LAG RC 1b0 ADC COMP1 Threshold Flag 1b0 No threshold crossing detected 1b1 Selected ADC measurement crossed condition set by 1_ADCALARM_ABOVE bit 5 COMP2_ALARM_FLAG RC 1b0 ADC COMP2 Threshold Flag 1b0...

Page 47: ...red 1b1 Watchdog Timer expired 5 SAFETY_TMR_FAULT_F LAG RC 1b0 Safety Timer Fault Flag 1b0 Safety Timer not expired 1b1 Safety Timer Expired 4 LDO_OCP_FAULT_FLAG RC 1b0 LDO Over Current Fault 1b0 LDO...

Page 48: ...1 Interrupt Masked 5 CHARGE_DONE_MASK R W 1b0 Mask for CHARGE_DONE interrupt 1b0 Interrupt Not Masked 1b1 Interrupt Masked 4 IINLIM_ACTIVE_MASK R W 1b0 Mask for IINLIM_ACTIVE interrupt 1b0 Interrupt N...

Page 49: ...1b0 Reserved 5 BAT_OCP_FAULT_MASK R W 1b0 Mask for BAT_OCP_FAULT interrupt 1b0 Interrupt Not Masked 1b1 Interrupt Masked 4 BAT_UVLO_FAULT_MAS K R W 1b0 Mask for BAT_UVLO_FAULT interrupt 1b0 Interrupt...

Page 50: ...nterrupt 1b0 Interrupt Not Masked 1b1 Interrupt Masked 6 COMP1_ALARM_MASK R W 1b1 Mask for COMP1_ALARM Interrupt 1b0 Interrupt Not Masked 1b1 Interrupt Masked 5 COMP2_ALARM_MASK R W 1b1 Mask for COMP2...

Page 51: ...ked 1b1 Interrupt Masked 5 SAFETY_TMR_FAULT_M ASK R W 1b0 Mask for SAFETY_TIMER_FAULT Interrupt 1b0 Interrupt Not Masked 1b1 Interrupt Masked 4 LDO_OCP_FAULT_MASK R W 1b0 Mask for LDO_OCP_FAULT Interr...

Page 52: ...able 9 21 VBAT_CTRL Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R W 1b0 Reserved 6 0 VBAT_REG_6 0 R W 7b0111100 Battery Regulation Voltage 4 2 V default VBATREG 3 6 V VBAT_...

Page 53: ...1000 Table 9 22 ICHG_CTRL Register Field Descriptions Bit Field Type Reset Description 7 0 ICHG_7 0 R W 8b00001000 Fast Charge Current 10 mA default Fast Charge Current 1 25 mA x ICHG code ICHARGE_RAN...

Page 54: ...Type Reset Description 7 ICHARGE_RANGE R W 1b0 Charge Current Step 1b0 1 25 mA step 318 75 mA max charge current 1b1 2 5 mA step 500 mA max charge current 6 5 RESERVED R W 2b00 Reserved 4 0 IPRECHG_4...

Page 55: ...pe Reset Description 7 6 RESERVED R W 2b00 Reserved 5 1 ITERM_4 0 R W 5b01010 Termination Current 10 of ICHRG default Programmable Range 1 to 31 of ICHRG 5b00000 Do not Use 5b00001 1 of ICHRG 5b00010...

Page 56: ...ption 7 6 RESERVED R W 2b00 Reserved 5 VLOWV_SEL R W 1b0 Pre charge to Fast Charge Threshold 1b0 3 0 V 1b1 2 8 V 4 3 IBAT_OCP_ILIM_1 0 R W 2b00 Battery Over Current Protection Threshold 2b00 1200 mA 2...

Page 57: ...bled 1b1 TS function enabled 6 TS_CONTROL_MODE R W 1b0 TS Function Control Mode 1b0 Custom JEITA 1b1 Disable charging on HOT COLD Only 5 VRH_THRESH R W 1b0 Recharge Voltage Threshold 1b0 140 mV 1b1 20...

Page 58: ...NDPM Function 1b0 VINDPM Enabled 1b1 VINDPM Disabled 6 4 VINPDM_2 0 R W 3b000 VINDPM Level Selection 3b000 4 2 V 3b001 4 3 V 3b010 4 4 V 3b011 4 5 V 3b100 4 6 V 3b101 4 7 V 3b110 4 8 V 3b111 4 9 V 3 D...

Page 59: ...Table 9 28 ILIMCTRL Register Field Descriptions Bit Field Type Reset Description 7 3 RESERVED R W 5b00000 Reserved 2 0 ILIM_2 0 R W 3b001 Input Current Limit Level Selection 3b000 50 mA 3b001 100 mA 3...

Page 60: ...Field Descriptions Bit Field Type Reset Description 7 EN_LS_LDO R W 1b1 LS LDO Enable 1b0 Disable LS LDO 1b1 Enable LS LDO 6 2 VLDO_4 0 R W 5b01100 LDO output voltage setting 1 8 V default LDO Voltag...

Page 61: ...eset sent when MR reset time is met regardless of VIN state 1b1 Reset sent when MR reset is met and Vin is valid 6 MR_WAKE1_TIMER R W 1b0 Wake 1 Timer setting 1b0 125 ms 1b1 500 ms 5 MR_WAKE2_TIMER R...

Page 62: ...VIN is not valid and MR is high 6 RESERVED R W 1b0 Reserved 5 4 AUTOWAKE_1 0 R W 2b01 Auto wakeup Timer TRESTART for MR HW Reset 2b00 0 6 s 2b01 1 2 s 2b10 2 4 s 2b11 5 s 3 RESERVED R W 1b0 Reserved 2...

Page 63: ...Pin Mode of Operation 1b0 General Purpose ADC input no Internal biasing 1b1 10K NTC ADC input 80 A biasing 4 RESERVED R W 1b0 Reserved 3 2 PG_MODE_1 0 R W 2b00 PG Pin Mode of Operation 2b00 VIN Power...

Page 64: ...0 Reserved 4 GPO_PG R W 1b0 PG General Purpose Output State Control 1b0 Pulled Down 1b1 High Z 3 2 RESERVED R W 2b00 Reserved 1 HWRESET_14S_WD R W 1b0 Enable for 14 second I2C watchdog timer for HW Re...

Page 65: ...ent done when ADC_CONV_START is set 2b01 Continuous 2b10 Every 1 second 2b11 Every 1 minute 5 ADC_CONV_START R W 1b0 ADC Conversion Start Trigger Bit goes back to 0 when conversion is complete 1b0 No...

Page 66: ...ield Type Reset Description 7 5 ADC_COMP2_2 0 R W 3b010 ADC Channel for Comparator 2 3b000 Disabled 3b001 ADCIN 3b010 TS 3b011 VBAT 3b100 ICHARGE 3b101 VIN 3b110 PMID 3b111 IIN 4 2 ADC_COMP3_2 0 R W 3...

Page 67: ...ure 9 42 ADC_DATA_VBAT_M Register 7 6 5 4 3 2 1 0 VBAT_ADC_15 8 R W X Table 9 36 ADC_DATA_VBAT_M Register Field Descriptions Bit Field Type Reset Description 7 0 VBAT_ADC_15 8 R W X ADC VBAT Measureme...

Page 68: ...gure 9 43 ADC_DATA_VBAT_L Register 7 6 5 4 3 2 1 0 VBAT_ADC_7 0 R W X Table 9 37 ADC_DATA_VBAT_L Register Field Descriptions Bit Field Type Reset Description 7 0 VBAT_ADC_7 0 R W X ADC VBAT Measuremen...

Page 69: ...Figure 9 44 ADC_DATA_TS_M Register 7 6 5 4 3 2 1 0 TS_ADC_15 8 R W X Table 9 38 ADC_DATA_TS_M Register Field Descriptions Bit Field Type Reset Description 7 0 TS_ADC_15 8 R W X ADC TS Measurement MSB...

Page 70: ...Figure 9 45 ADC_DATA_TS_L Register 7 6 5 4 3 2 1 0 TS_ADC_7 0 R W X Table 9 39 ADC_DATA_TS_L Register Field Descriptions Bit Field Type Reset Description 7 0 TS_ADC_7 0 R W X ADC TS Measurement LSB B...

Page 71: ...ure 9 46 ADC_DATA_ICHG_M Register 7 6 5 4 3 2 1 0 ICHG_ADC_15 8 R W X Table 9 40 ADC_DATA_ICHG_M Register Field Descriptions Bit Field Type Reset Description 7 0 ICHG_ADC_15 8 R W X ADC ICHG Measureme...

Page 72: ...gure 9 47 ADC_DATA_ICHG_L Register 7 6 5 4 3 2 1 0 ICHG_ADC_7 0 R W X Table 9 41 ADC_DATA_ICHG_L Register Field Descriptions Bit Field Type Reset Description 7 0 ICHG_ADC_7 0 R W X ADC ICHG Measuremen...

Page 73: ...e 9 48 ADC_DATA_ADCIN_M Register 7 6 5 4 3 2 1 0 ADCIN_ADC_15 8 R W X Table 9 42 ADC_DATA_ADCIN_M Register Field Descriptions Bit Field Type Reset Description 7 0 ADCIN_ADC_15 8 R W X ADC ADCIN Measur...

Page 74: ...re 9 49 ADC_DATA_ADCIN_L Register 7 6 5 4 3 2 1 0 ADCIN_ADC_7 0 R W X Table 9 43 ADC_DATA_ADCIN_L Register Field Descriptions Bit Field Type Reset Description 7 0 ADCIN_ADC_7 0 R W X ADC ADCIN Measure...

Page 75: ...gure 9 50 ADC_DATA_VIN_M Register 7 6 5 4 3 2 1 0 VIN_ADC_15 8 R W X Table 9 44 ADC_DATA_VIN_M Register Field Descriptions Bit Field Type Reset Description 7 0 VIN_ADC_15 8 R W X ADC VIN Measurement M...

Page 76: ...igure 9 51 ADC_DATA_VIN_L Register 7 6 5 4 3 2 1 0 VIN_ADC_7 0 R W X Table 9 45 ADC_DATA_VIN_L Register Field Descriptions Bit Field Type Reset Description 7 0 VIN_ADC_7 0 R W X ADC VIN Measurement LS...

Page 77: ...ure 9 52 ADC_DATA_PMID_M Register 7 6 5 4 3 2 1 0 PMID_ADC_15 8 R W X Table 9 46 ADC_DATA_PMID_M Register Field Descriptions Bit Field Type Reset Description 7 0 PMID_ADC_15 8 R W X ADC PMID Measureme...

Page 78: ...gure 9 53 ADC_DATA_PMID_L Register 7 6 5 4 3 2 1 0 PMID_ADC_7 0 R W X Table 9 47 ADC_DATA_PMID_L Register Field Descriptions Bit Field Type Reset Description 7 0 PMID_ADC_7 0 R W X ADC PMID Measuremen...

Page 79: ...gure 9 54 ADC_DATA_IIN_M Register 7 6 5 4 3 2 1 0 IIN_ADC_15 8 R W X Table 9 48 ADC_DATA_IIN_M Register Field Descriptions Bit Field Type Reset Description 7 0 IIN_ADC_15 8 R W X ADC IIN Measurement M...

Page 80: ...igure 9 55 ADC_DATA_IIN_L Register 7 6 5 4 3 2 1 0 IIN_ADC_7 0 R W X Table 9 49 ADC_DATA_IIN_L Register Field Descriptions Bit Field Type Reset Description 7 0 IIN_ADC_7 0 R W X ADC IIN Measurement LS...

Page 81: ...LARM_COMP1_M Register 7 6 5 4 3 2 1 0 1_ADCALARM_15 8 R W 8b00100011 Table 9 50 ADCALARM_COMP1_M Register Field Descriptions Bit Field Type Reset Description 7 0 1_ADCALARM_15 8 R W 8b00100011 ADC Com...

Page 82: ...Descriptions Bit Field Type Reset Description 7 4 1_ADCALARM_7 4 R W 4b0010 ADC Comparator 1 Threshold LSB 3 1_ADCALARM_ABOVE R W 1b0 ADC Comparator1 Polarity 1b0 Set Flag and send interrupt if ADC me...

Page 83: ...LARM_COMP2_M Register 7 6 5 4 3 2 1 0 2_ADCALARM_15 8 R W 8b00111000 Table 9 52 ADCALARM_COMP2_M Register Field Descriptions Bit Field Type Reset Description 7 0 2_ADCALARM_15 8 R W 8b00111000 ADC Com...

Page 84: ...escriptions Bit Field Type Reset Description 7 4 2_ADCALARM_7 4 R W 4b1001 ADC Comparator 2 Threshold LSB 3 2_ADCALARM_ABOVE R W 1b0 ADC Comparator 2 Polarity 1b0 Set Flag and send interrupt if ADC me...

Page 85: ...LARM_COMP3_M Register 7 6 5 4 3 2 1 0 3_ADCALARM_15 8 R W 8b00000000 Table 9 54 ADCALARM_COMP3_M Register Field Descriptions Bit Field Type Reset Description 7 0 3_ADCALARM_15 8 R W 8b00000000 ADC Com...

Page 86: ...escriptions Bit Field Type Reset Description 7 4 3_ADCALARM_7 4 R W 4b0000 ADC Comparator 3 Threshold LSB 3 3_ADCALARM_ABOVE R W 1b0 ADC Comparator 3 Polarity 1b0 Set Flag and send interrupt if ADC me...

Page 87: ...easurement disabled 1b1 ADC measurement enabled 5 EN_ICHG_READ R W 1b0 Enable measurement for Charge Current Channel 1b0 ADC measurement disabled 1b1 ADC measurement enabled 4 EN_VIN_READ R W 1b0 Enab...

Page 88: ...3b011 Reduced target battery voltage during Warm 3b000 No reduction 3b001 VBAT_REG 50 mV 3b010 VBAT_REG 100 mV 3b011 VBAT_REG 150 mV 3b100 VBAT_REG 200 mV 3b101 VBAT_REG 250 mV 3b110 VBAT_REG 300 mV...

Page 89: ...b01111100 Table 9 58 TS_COLD Register Field Descriptions Bit Field Type Reset Description 7 0 TS_COLD_7 0 R W 8b01111100 TS Cold Threshold 1b 4 688 mV 10b 9 375 mV 100b 18 75 mV 1000b 37 5 mV 10000b 7...

Page 90: ...b01101101 Table 9 59 TS_COOL Register Field Descriptions Bit Field Type Reset Description 7 0 TS_COOL_7 0 R W 8b01101101 TS Cool Threshold 1b 4 688 mV 10b 9 375 mV 100b 18 75 mV 1000b 37 5 mV 10000b 7...

Page 91: ...b00111000 Table 9 60 TS_WARM Register Field Descriptions Bit Field Type Reset Description 7 0 TS_WARM_7 0 R W 8b00111000 TS Warm Threshold 1b 4 688 mV 10b 9 375 mV 100b 18 75 mV 1000b 37 5 mV 10000b 7...

Page 92: ...00100111 Table 9 61 TS_HOT Register Field Descriptions Bit Field Type Reset Description 7 0 TS_HOT_7 0 R W 8b00100111 TS Hot Threshold 1b 4 688 mV 10b 9 375 mV 100b 18 75 mV 1000b 37 5 mV 10000b 75 mV...

Page 93: ...68 DEVICE_ID Register 7 6 5 4 3 2 1 0 DEVICE_ID_7 0 R 8b00111100 Table 9 62 DEVICE_ID Register Field Descriptions Bit Field Type Reset Description 7 0 DEVICE_ID_7 0 R 8b00111100 Device ID 111100b BQ25...

Page 94: ...monitor the battery temperature and control charging as desired The system designer may connect the MR input to a push button to send interrupts to the host as the button is pressed or to allow the a...

Page 95: ...ing must be higher than 1 F to ensure stability The VINLS input bypass capacitor value should match or exceed the LDO output capacitor value 10 2 2 3 TS A 10 K NTC should be connected in parallel to a...

Page 96: ...n To Ship Mode on Battery Insertion with No IN Supply VIN 0V VBAT 3 6V Figure 10 5 Power Up from Ship Mode with MR Press VIN 0V VBAT 3 6V Figure 10 6 HW Reset on MR Long Button Press VIN 0V VBAT 3 6V...

Page 97: ...Good Function IN Supply Insertion VIN 5V VBAT 3 6V Figure 10 11 PG Power Good Function IN Supply Removal VIN 5V VBAT 3 6V Figure 10 12 PG MR Level Shift Function MR Rising VBAT 3 6V Figure 10 13 PG MR...

Page 98: ...e Through I2C EN_LS_LDO VIN 0V VBAT 3 6V VINLS VPMID Figure 10 17 LDO Load Transient VLDO 1 8V VIN 0V VBAT 2 4V VINLS VPMID Figure 10 18 LDO Load Transient VLDO 1 8V VIN 0V VBAT 3 8V VINLS VPMID Figur...

Page 99: ...DO Load Transient VLDO 1 2V VIN 5V Figure 10 21 TS Biasing and Voltage Behavior when VIN is Present www ti com BQ25157 SLUSEC5 DECEMBER 2020 Copyright 2020 Texas Instruments Incorporated Submit Docume...

Page 100: ...between 3 4 V and 6 2 V with at least 600 mA rating The battery voltage must be higher than 2 4 V or VBATUVLO to ensure proper operation BQ25157 SLUSEC5 DECEMBER 2020 www ti com 100 Submit Document F...

Page 101: ...ssible and GND or ground plane A bypass capacitor from VINLS to GND is recommended to be placed as close as possible to the VINLS bump 12 2 Layout Example IN PG MR VDD VIO BAT PMID BAT CE NC INT LP SD...

Page 102: ...for fast verified answers and design help straight from the experts Search existing answers or ask your own question to get the quick design help you need Linked content is provided AS IS by the respe...

Page 103: ...t current data available for the designated devices This data is subject to change without notice and revision of this document For browser based versions of this data sheet refer to the left hand nav...

Page 104: ...tardants must also meet the 1000ppm threshold requirement 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature 4 T...

Page 105: ...e Package Type Package Drawing Pins SPQ Reel Diameter mm Reel Width W1 mm A0 mm B0 mm K0 mm P1 mm W mm Pin1 Quadrant BQ25157YFPR DSBGA YFP 20 3000 180 0 8 4 1 77 2 17 0 62 4 0 8 0 Q1 PACKAGE MATERIALS...

Page 106: ...ons are nominal Device Package Type Package Drawing Pins SPQ Length mm Width mm Height mm BQ25157YFPR DSBGA YFP 20 3000 182 0 182 0 20 0 PACKAGE MATERIALS INFORMATION www ti com 20 Dec 2020 Pack Mater...

Page 107: ...D Max E Max 2 045 mm Min 1 645 mm Min 1 985 mm 1 585 mm...

Page 108: ......

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Page 110: ...e resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reprod...

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