Printed-Circuit Board Layout Guideline
6. Measure:
Measure on VM#3
→
V(J5(SYS), J9(GND)) = 3.7V ±150 mV.
Observe
→
D1 and D2 are on.
7. Move JP2 (CD) = HI.
8. Measure on VM#3
→
V(J5(SYS), J9(GND)) = 0 V.
9. Disable PS #1 and disconnect electronic load or resistor box and CM #3 from the HPA758 board.
2.4.2
Charge Voltage and Current Regulation of USB
1. Be sure to follow
steps .
2. Connect the USB port of the HPA172 kit to the USB port of the computer.
3. Connect the output of Power Supply #1 (PS #1) in series with current meter (multimeter) #1 (CM #1) to
J1 and J3 or J2 (USB, GND).
4. Connect a voltage meter 1 (VM #1) across J1 or TP2 and J3 (USB, GND).
5. Move JP2 (CD) to HI.
6. Turn on PS #1 and PS #2.
7. Return JP2 (CD) to LO.
8. Software setup:
•
Press the READ button to obtain the current settings.
•
Set Write On Change to ON if not already set.
•
Set Reset Watchdog Timer to update every 5 seconds.
•
Uncheck Disable Charging if checked.
•
Check Enable STAT/INT Outputs.
•
Set Battery Regulation Voltage to 4.20 V.
•
Set USB Input Current Limit to 1500 mA.
•
Set Charge Current to 1000 mA.
•
Click the READ button at the top of the window, and confirm that the previous settings remain.
9. Adjust PS #2 so that the voltage measured by VM #2, across BAT and GND, measures 3.2 V ± 50 mV.
10. Adjust the power supply so that VM #1 still reads 6 V ± 100 mV if necessary then
Measure on CM#2
→
I
CHRG
= 1000 mA ± 100 mA
Measure on CM#1
→
I
IN
< 850 mA
Observe
→
D1 and D2 are on.
11. Turn off PS #1 and PS #2.
2.4.3
Helpful hints
1. Observe the taper current as the battery voltage approaches the set regulation voltage, allow the
battery to charge or, if using BAT_Load (PR1010), slowly increase the PS #2 voltage powering
BAT_Load (PR1010). Use VM #2 across BAT and GND to measure the battery voltage seen by the IC.
2. Observe the V
INDPM
function, lower the current limit on PS #1.
3. Observe battery supplement mode, apply a resistive load across SYS and GND that is higher than the
maximum charge current.
3
Printed-Circuit Board Layout Guideline
1. To obtain optimal performance, the power input capacitors, connected from the PMID input to PGND,
must be placed as close as possible to the bq2427x.
2. Place a 4.7-µF input capacitor as close to PMID pin and PGND pin as possible to make the high-
frequency, current-loop area as small as possible. Place 1-µF input capacitor GNDs as close to the
respective PMID capacitor GND and PGND pins as possible to minimize the ground difference
between the input and PMID.
11
SLUU924 – April 2012
QFN-Packaged bq24270/271 Evaluation Modules
Copyright © 2012, Texas Instruments Incorporated
