Cff
t
t
ON (max)
(R2//R3)
FB
SW
BST
VCC
ISEN
SGND
VIN
R1
43.2k
SS
RTN
Gnd
D1
A1
A2
On
Timer
Minimum
Off
Timer
Logic
Regulation
Comparator
B3
A3
Current Limit
Detect
D3
C3
0.18
:
C1
IN
Gnd
C2
1
P
F
8
V to
40V
RON/SD
C6
0.022
P
F
0.1
P
F
C3
1
P
F
0.1
P
F
C4
B1
V
IN
V
OUT
C5
D1
D2
C1
2.49k
R3
2.49k
R2
1000 pF
P
F
10
P
F
10
5V
LM34919
15
P
H
L1
R6 0
:
C8
C7
2.5V
0.022
P
F
Cff
R4
FB
SW
BST
VCC
ISEN
SGND
VIN
R1
43.2k
SS
RTN
Gnd
D1
A1
A2
On
Timer
Minimum
Off
Timer
Logic
Regulation
Comparator
B3
A3
Current Limit
Detect
D3
C3
0.39
:
C1
IN
Gnd
C2
1
P
F
8
V to
40V
RON/SD
C6
0.022
P
F
0.1
P
F
C3
1
P
F
0.1
P
F
C4
B1
V
IN
V
OUT
C5
D1
D2
C1
2.49k
R3
2.49k
R2
P
F
10
P
F
10
5V
LM34919
15
P
H
L1
R6 0
:
C8
C7
2.5V
0.022
P
F
R4
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Output Ripple Control
Figure 2. Lowest Cost Configuration
Option B) Intermediate Ripple Configuration: This configuration generates less ripple at V
OUT
than
option A above by the addition of one capacitor (Cff) across R2, as shown in
Figure 3
.
Figure 3. Intermediate Ripple Configuration
Since the output ripple is passed by Cff to the FB pin with little or no attenuation, R4 can be reduced so
the minimum ripple at V
OUT
is
≊
25 mVp-p. The minimum value for Cff is calculated from:
(2)
where t
ON(max)
is the maximum on-time (at minimum V
IN
), and R2//R3 is the parallel equivalent of the
feedback resistors. See
Figure 8
.
Option C) Minimum Ripple Configuration: To obtain minimum ripple at V
OUT
, R4 is set to 0
Ω
, and R5,
C9, and C10 are added to generate the required ripple for the FB pin. In this configuration, the output
ripple is determined primarily by the ESR of the output capacitance and the inductor’s ripple current.
The ripple voltage required by the FB pin is generated by R5, C10, and C9 since the SW pin switches
from -1V to V
IN
, and the right end of C10 is a virtual ground. The values for R5 and C10 are chosen to
generate a 50-100 mVp-p triangle waveform at their junction. That triangle wave is then coupled to the FB
pin through C9. The following procedure is used to calculate values for R5, C10 and C9:
3
SNVA250A – June 2007 – Revised April 2013
AN-1650 LM34919 Evaluation Board
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