Connection and Proper Test Methods
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Figure 3. Evaluation Board Schematic Part 3: the PoE Circuit
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Connection and Proper Test Methods
Figure 4
shows a photo of the evaluation board with the connection ports indicated. The PoE circuit
occupies the lower part of the board within the rectangular outline. The RJ45 connectors, Ethernet
magnetics and PHY circuit are placed in the upper area of the board.
The following are the seven connections:
•
J1, a 42 pin MII Connector for the Ethernet media independent interface.
•
JE4 through JE7, double pairs of connection pins for the 3.3V output. JE4 and JE5 of are the high
potential pins
•
J13, a regular RJ45 connector on the -E version board for PoE input and data link
•
UE13, Bel Stewart Integrated RJ45 connector on the -I version board for PoE input and data link
•
TP7 and TP8, a pair of pins for quick PoE input connection to a bench power supply. TP7 is the high
potential pin
•
P1, a PJ102A power jack, for Auxiliary (AUX) power input. The center pin of P1 is the high potential pin
•
TP3 and TP4, a pair of pins for quick AUX power input connection to a bench power supply. TP3 is the
high potential pin
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AN-1521 POEPHYTEREV-I / -E Evaluation Board
SNOA476C – October 2006 – Revised April 2013
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