PoE Performance Characteristics
www.ti.com
Horizontal Resolution: 5 ms/div.
Trace 1: AUX input voltage (VIN to RTN pins). 10V/div.
Trace 2: The 3.3V output voltage. 2V/div.
Trace 3: The input current. 1A/div.
Figure 6. AUX Power Up Sequence
22.3 Output Dead Short Fault Response and Over Current Protection
The evaluation board survives the output dead short condition by running into re-try mode (hiccup) or
cycle-by-cycle peak current limit mode, depending on the input voltage condition when the fault occurs.
Applying a dead short to the +3.3V line causes a number of protection mechanisms to take place
sequentially. They are:
1. The feedback signal increases the duty cycle in an attempt to maintain the output voltage. This initiates
cycle-by-cycle over-current limiting which turns off the main switch when the current sense (CS) pin
exceeds the current limit threshold.
2. The current in the internal hot swap MOSFET increases until it is current limited around 800 mA. Some
overshoot in the current will be observed, as it takes time for the current limit amplifier to react and
change the operating mode of the MOSFET.
3. Because linear current limiting is accomplished by driving the MOSET into the saturation region, the
drain voltage (RTN pin) rises. When it reaches 2.5V with respect to VEE, power good is de-asserted
and the nPGOOD pin voltage rises.
4. The de-assertion of power good causes the discharge of the soft-start capacitor, which disables all
switching action in the dc-dc converter.
5. Once the switching stops, the current in the internal MOSFET will decrease and the drain voltage will
fall back below 1.5V with respect to VEE. When power good is re-asserted, the dc-dc converter will
automatically restart with a new soft-start sequence.
Figure 7
and
Figure 8
show cycle-by-cycle peak current limit in response to an output dead short with a
24V AUX input and 48V PoE input, respectively. The short-circuit condition results in a peak current of
about 3.2A in the primary circuit. This peak current produces about 0.5V peak at the CS pin, initiating
cycle-by-cycle peak current limit mode. The duty cycle is thus greatly reduced, which in turn limits the AUX
input dc current to about 0.39A, and the PoE input dc current to about 0.16A, respectively.
12
AN-1521 POEPHYTEREV-I / -E Evaluation Board
SNOA476C – October 2006 – Revised April 2013
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated