Texas Instruments AMC1210EVM, User Manual

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1.2 Digital Interface
EVM Overview
J07 is a dummy connector for mechanical stability purposes only.
The inputs of the ADS104 are secured against voltage peaks through clamp diodes.
The AMC1210 modular EVM is designed for easy interfacing to multiple control platforms. Through the
connectors J09 and J08, the AMC1210 can be configured through a SPI interface from a F2812 type DSK.
Signal Description
J08.1 CLK System clock
J08.2 SH2 Sample-and-hold signal 2
J08.7 SH1 Sample-and-hold signal 1
J09.3 SPICLK SPI clock
J09.7 SPISTE SPI frame sync
J09.11 SPIDIN SPI input data
J09.13 SPIDOUT SPI output data
J09.14 RST Asynchronous reset input
J09.15 ACK Data acknowledge output
J09.19 INT Interrupt output
Through J08, J09, J10, and J11, the AMC1210 can be configured through one of three different
multiplexed parallel interface modes.
Signal
(1)
Description
J08.1 CLK System clock
J08.2 SH2 Sample-and-hold signal 2
J08.7 SH1 Sample-and-hold signal 1
J09.14 RST Asynchronous reset input
J10.1 CS Chip select
J10.3 WR Write signal
J10.5 RD Read signal
J11.1 AD0 Address/databus bit 0 (LSB)
J11.3 AD1 Address/databus bit 1
J11.5 AD2 Address/databus bit 2
J11.7 AD3 Address/databus bit 3
J11.9 AD4 Address/databus bit 4
J11.11 AD5 Address/databus bit 5
J11.13 AD6 Address/databus bit 6
J11.15 AD7 Address/databus bit 7 (MSB)
J09.15 ACK Data acknowledge output
J09.17 ALE Address latch enable
J09.19 INT Interrupt output
(1)
All even pin numbers of the connectors J10, J11, J12, and J15 are grounded.
All digital signals can be accessed through the connectors J12, J13, J14, and J15 on the top of the
AMC1210 modular EVM. The different signals are placed at the same position as the bottom-mounted
connectors, see the preceding tables.
For higher frequencies on the CLK input of the AMC1210, it could be possible to reduce the value of the
series resistor R47.
AMC1210EVM 2 SLAU185 – August 2006
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