Motorola MVME6100-0161 Programmer'S Reference Manual Download

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MVME6100

Single-Board Computer

Programmer’s Reference

Guide

V6100A/PG1

July 2004 Edition

Summary of Contents for MVME6100-0161

Page 1: ...MVME6100 Single Board Computer Programmer s Reference Guide V6100A PG1 July 2004 Edition ...

Page 2: ...ted in the United States of America Motorola and the stylized M logo are trademarks of Motorola Inc registered in the U S Patent and Trademark Office All other product or service names mentioned in this document are the property of their respective owners ...

Page 3: ...the Equipment Operating personnel must not remove equipment covers Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Service personnel should not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power ...

Page 4: ...losion if battery is replaced incorrectly Replace battery only with the same or equivalent type recommended by the equipment manufacturer Dispose of used batteries according to the manufacturer s instructions Attention Caution Il y a danger d explosion s il y a remplacement incorrect de la batterie Remplacer uniquement avec une batterie du même type ou d un type équivalent recommandé par le constr...

Page 5: ...nd Methods of Measurement of Radio Interference Characteristics of Information Technology Equipment this product tested to Equipment Class A EN55024 Information technology equipment Immunity characteristics Limits and methods of measurement Board products are tested in a representative system to show compliance with the above mentioned requirements A proper installation in a CE marked system will ...

Page 6: ...ola Inc It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not available in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Limited and Restricted Rights Legend If the docu...

Page 7: ...Register 1 1 11 System Status Register 2 1 13 System Status Register 3 1 15 Presence Detect Register 1 16 Configuration Header Switch Register S1 1 17 Time Base Enable Register 1 19 Quad Universal Asynchronous Receiver Transmitter UART 1 19 Real Time Clock and NVRAM 1 20 CHAPTER 2 Programming Details Introduction 2 1 MV64360 Multi Purpose Port Configuration 2 1 MV64360 Reset Configuration 2 3 Flas...

Page 8: ... PCI Configuration Space 2 13 PCI Arbitration Assignments for MV64360 ASIC 2 14 PCI Bus 1 Local Bus PMC Expansion Slots 2 14 PCI Bus 0 Local Bus Devices 2 15 Tsi148 ASIC 2 15 PCI6520 PMCSpan Bridge 2 15 MV64360 Interrupt Controller 2 16 MV64360 Endian Issues 2 18 APPENDIX A Related Documentation Motorola Computer Group Documents A 1 Manufacturers Documents A 2 Related Specifications A 5 ...

Page 9: ...ix Figure 1 1 MVME6100 Board Layout Diagram 1 4 Figure 2 1 PCI Bus 1 Local Bus PMC Expansion Slots 2 15 List of Figures ...

Page 10: ... Table 1 11 Configuration Header Switch Register 1 17 Table 1 12 TBEN Register 1 19 Table 1 13 M48T37V Access 1 20 Table 2 1 MV64360 MPP Pin Function Assignments 2 2 Table 2 2 MV64360 Power Up Configuration Settings 2 4 Table 2 3 M48T37V Access 2 9 Table 2 4 I2C Bus Device Addressing 2 10 Table 2 5 Device Bank Assignments 2 12 Table 2 6 IDSEL Mapping for PCI Devices 2 13 Table 2 7 PCI Arbitration ...

Page 11: ...al information about the MVME6100 products As of the printing date of this manual the MVME6100 supports the models listed below Model Number Description MVME6100 0161 1 267 GHz MPC7457 processor 512MB DDR memory 128MB Flash Scanbe handles MVME6100 0163 1 267 GHz MPC7457 processor 512MB DDR memory 128MB Flash IEEE handles MVME6100 0171 1 267 GHz MPC7457 processor 1GB DDR memory 128MB Flash Scanbe h...

Page 12: ...ppendix A Related Documentation provides a listing of related Motorola manuals vendor documentation and industry specifications Comments and Suggestions Motorola welcomes and appreciates your comments on its documentation We want to know what you think about our manuals and how we can make them better Mail comments to Motorola Computer Group Reader Comments DW164 2900 S Diablo Way Tempe Arizona 85...

Page 13: ...names of variables to which you assign values for function parameters and for structure names and fields Italic is also used for comments in screen displays and examples and to introduce new terms courier is used for system output for example screen displays reports examples and system prompts Enter Return or CR represents the carriage return or Enter key Ctrl represents the Control key Execute co...

Page 14: ...I O memory maps Note Programmable registers in the MV64360 system controller are documented in a separate publication and obtainable from Motorola Computer Group by contacting your Field Area Engineer Refer to Appendix A Related Documentation for more information on obtaining this documentation Overview The MVME6100 is a single board computer based on the PowerPC MPC7457 processor the Marvell MV64...

Page 15: ...otect scheme Bank B top 1MB block can be write protected through software hardware write protect control System Memory Two banks on board for up to 2GB using 256Mb or 512Mb devices Bus clock frequency at 133 MHz Memory Controller PCI Host Bridge Dual 10 100 1000 Ethernet Interrupt Controller PCI Interface I2 C Interface Provided by Marvell MV64360 system controller NVRAM Real Time Clock Watchdog T...

Page 16: ...and 32 bit single cycle data transfers 8 bit 16 bit 32 bit and 64 bit block transfers Supports SCT BLT MBLT 2eVME and 2eSST protocols 8 entry command and 4KB data write post buffer 4KB read ahead buffer PMCspan Support One PMCspan slot Supports 33 66 MHz 32 64 bit PCI bus Access through PCI6520 bridge to PMCspan Form Factor Standard 6U VME Miscellaneous Combined reset and abort switch Status LEDs ...

Page 17: ...100 Board Layout Diagram 4248 0504 10 100 1000 DEBUG ABT RST LAN 2 LAN 1 J42 J8 J30 U20 J3 J19 J13 J14 J11 J12 J23 J24 J21 J22 P1 P2 U21 PCI MEZZANINE CARD PCI MEZZANINE CARD J4 U12 10 100 1000 J93 J9 J29 U1 J7 PMC IPMC U32 U7 U6 U5 U3 U4 U11 U10 U9 U8 U13 U18 U14 U15 U22 U30 U19 U17 U16 U23 U27 U25 ...

Page 18: ...ddress Map Processor Address Size Definition Notes Start End 0000 0000 007F FFFF 8M DRAM Bank 0 0080 0000 00FF FFFF 8M DRAM Bank 1 0100 0000 017F FFFF 8M DRAM Bank 2 0180 0000 01FF FFFF 8M DRAM Bank 3 0200 0000 0FFF FFFF 224M Unassigned 1000 0000 11FF FFFF 32M PCI Bus 0 I O Space 1200 0000 13FF FFFF 32M PCI Bus 0 Memory Space 0 1400 0000 1BFF FFFF 128M Unassigned 1C00 0000 1C7F FFFF 8M Device CS0 ...

Page 19: ...d F100 0000 F100 FFFF 64K Internal Registers See Note F101 0000 F1FF FFFF 16M 64K Unassigned F200 0000 F3FF FFFF 32M PCI Bus 0 Memory Space 1 F400 0000 F5FF FFFF 32M PCI Bus 0 Memory Space 2 F600 0000 F7FF FFFF 32M PCI Bus 0 Memory Space 3 F800 0000 FEFF FFFF 112M Unassigned FF00 0000 FF7F FFFF 8M Device CS3 FC00 0000 FFFF FFFF 64M Boot Flash Bank A or B depending on S4 3 switch setting Table 1 2 ...

Page 20: ...ocessor Address Size Definition Notes Start End 0000 0000 top_dram 1 dram_size System Memory onboard DRAM 8000 0000 DFFF FFFF 1536M PCI Bus 0 and or VME Memory Space E000 0000 EFFF FFFF 256M PCI Bus 1 Memory Space F000 0000 F07F FFFF 8M PCI Bus 1 I O Space F080 0000 F0FF FFFF 8M PCI Bus 0 I O Space F100 0000 F10F FFFF 1M MV64360 Internal Registers See Note F110 0000 F11F FFFF 1M Device CS1 I O Sys...

Page 21: ...FFF 8M DRAM Bank 3 0200 0000 0FFF FFFF 224M Unassigned 1000 0000 11FF FFFF 32M PCI Bus 1 P2P I O Space 1200 0000 13FF FFFF 32M PCI Bus 1 P2P Memory Space 0 1400 0000 1400 FFFF 64K Internal Registers 1401 0000 1BFF FFFF 128M 64K Unassigned 1C00 0000 1C7F FFFF 8M Device CS0 1C80 0000 1CFF FFFF 8M Device CS1 1D00 0000 1DFF FFFF 16M Device CS2 1E00 0000 1FFF FFFF 32M Unassigned 2000 0000 21FF FFFF 32M...

Page 22: ...ystem I O Memory Map System resources including system control and status registers NVRAM RTC and the 16550 UART are mapped into a 1 MB address F200 0000 F3FF FFFF 32M PCI Bus 1 P2P Memory Space 1 F400 0000 FEFF FFFF 176M Unassigned FF00 0000 FF7F FFFF 8M Device CS3 FC00 0000 FFFF FFFF 64M Boot Flash Bank B Table 1 4 Default PCI Address Map continued PCI Address Size Definition Start End Table 1 5...

Page 23: ...tus Register 1 F110 0001 System Status Register 2 F110 0002 System Status Register 3 F110 0003 Reserved F110 0004 Presence Detect Register F110 0005 Software Readable Header Switch F110 0006 Timebase Enable Register F110 0008 F110 FFFF Reserved for onboard registers F111 0000 F111 7FFF M48T37V NVRAM RTC F112 0000 F112 0FFF COM 1 UART F112 1000 F112 0FFF COM 2 UART F112 2000 F112 0FFF Reserved unde...

Page 24: ...rrent state of the boot Flash bank select jumper A cleared condition indicates that Flash bank A is the boot bank A set condition indicates that Flash B is the boot bank SAFE_START ENV safe start This bit reflects the current state of the ENV safe start select jumper A set condition indicates that MOTLoad should provide the user the capability to select which Boot Image is used to boot the board c...

Page 25: ...e of the Flash Bank A StrataFlash device Status pins These two open drain output pins are wire ORed Refer to the appropriate Intel StrataFlash data sheet for a description on the function of the Status pin FUSE_STAT Fuse Status This bit indicates the status of the onboard fuses A cleared condition indicates that one of the fuses is open A set condition indicates that all fuses are functional SROM_...

Page 26: ...0 FLASHA_WP Software Flash Bank A Write Protect This bit is to provide software controlled protection against inadvertent writes to the expansion FLASH memory devices Clearing this bit and disabling the HW write protect will enable writes to the Bank A Flash devices This bit is set during reset and must be reset by the system software to enable writing of the flash devices Table 1 8 System Status ...

Page 27: ...tion against inadvertent writes to the Flash Bank B Top 1 MB 0xFFF00000 space Clearing this bit and disabling HW write protect will enable writes to the Bank B Flash Top 1MB boot block devices This bit is set during reset and must be reset by the system software to enable writing of the Flash Bank B boot block FBA_WP_HDR Hardware Flash Bank A write protect header status Read ONLY Hardware jumper c...

Page 28: ...ons BOARD_RESET Board Reset Setting this bit will force a hard reset of the MVME6100 board This bit will clear automatically when the board reset is complete This bit will always be cleared during a read Table 1 9 System Status Register 3 REG System Status Register 3 0xF1100002 BIT 7 6 5 4 3 2 1 0 FIELD BOARD_RESET RSVD RSVD RSVD RSVD RSVD RSVD RSVD OPER R W R R R R R R R RESET 0 0 0 0 0 0 0 0 ...

Page 29: ... module is not ready for enumeration The PrPMC software must assert EREADY for this bit to be set The purpose of EREADY is to provide a signaling method indicating that a non monarch vassal PrPMC is ready to be enumerated EREADY0 EREADY0 Indicates that the PrPMC module installed in PMC slot 1 is ready for enumeration when set If cleared the PrPMC module is not ready for enumeration The purpose of ...

Page 30: ...t If set there is no PMC module installed in slot 1 If cleared the PMC module is installed Configuration Header Switch Register S1 The MVME6100 board has an 8 bit header or switch that may be read by the software CFG 7 0 Configuration Bits 7 0 These bits reflect the position of the switch installed in the configuration header location A cleared condition Table 1 11 Configuration Header Switch Regi...

Page 31: ...at the switch is ON for the header position associated with that bit and a set condition indicates that the switch is OFF CFG_0 0 CFG_1 0 CFG_2 0 CFG_3 0 CFG_4 0 CFG_5 0 CFG_6 0 CFG_7 0 CFG_0 1 CFG_1 1 CFG_2 1 CFG_3 1 CFG_4 1 CFG_5 1 CFG_6 1 CFG_7 1 ON ON 1 1 16 16 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 ...

Page 32: ...ne EXAR ST16C554D Quad UART device connected to the MV64360 device controller bus to provide asynchronous debug ports The Quad UART supports up to four asynchronous serial ports of which two are used on the MVME6100 The ST16C554D is a universal asynchronous receiver and transmitter and is an enhanced UART with 16 byte FIFOs receive trigger levels and data rates up to 1 5 Mbps Onboard status regist...

Page 33: ...ard planar header for rear I O access via option inductors resistors Unused control inputs on COM1 and COM2 are wired active The reference clock frequency for the QUART is 1 8432 MHz All UART ports are capable of signaling at up to 115 Kbaud Real Time Clock and NVRAM The Real Time Clock NVRAM Watchdog Timer is implemented using a SGS Thompson M48T37V Timekeeper SRAM and M4T28 BR12SH1 SnapHat batte...

Page 34: ...on page 2 11 Temperature Sensor on page 2 11 MV64360 Device Controller Bank Assignments on page 2 11 MPC Bus and PCI Bus Arbitration on page 2 12 PCI Bus 0 and PCI Bus 1 Local Buses on page 2 12 MV64360 Interrupt Controller on page 2 16 MV64360 Endian Issues on page 2 18 MV64360 Multi Purpose Port Configuration The MV64360 contains a 32 bit multi purpose port MPP The MPP pins can be configured as ...

Page 35: ...errupt 7 I BCM5421S PHY interrupts ORed MPP 7 0 Interrupts 8 O PCI Bus 1 PMC slot 0 agent grant 9 I PCI Bus 1 PMC slot 0 agent request 10 O PCI Bus 1 PMC slot 1 agent grant 11 I PCI Bus 1 PMC slot 1 agent request 12 O PCI Bus 1 PMC slot 0 grant 13 I PCI Bus 1 PMC slot 0 request 14 O PCI Bus 1 PMC slot 1 grant 15 I PCI Bus 1 PMC slot 1 request MPP 15 8 PCI_1 Arbitration Request Grant Pairs 16 I PCI...

Page 36: ...Tempe LINT1 PMCspan INT 3 22 I PCI Bus 0 Interrupt PCI VME INT 2 Tempe LINT2 PMCspan INT 0 23 I PCI Bus 0 Interrupt PCI VME INT 3 Tempe LINT3 PMCspan INT 1 MPP 19 16 PCI_1 Interrupts MPP 23 20 PCI_0 Interrupts 24 O MV64360 SROM initialization active InitAct 25 O Watchdog Timer Expired output WDE 26 O Watchdog Timer NMI output WDNMI 27 I Reserved for future device interrupt 28 O Tempe ASIC VMEbus g...

Page 37: ...al registers or other system components i e devices on the PCI bus can be initialized Initialization takes place by sequentially reading 8 byte address data pairs from the SROM and writing the 32 bit data to the decoded 32 bit address until the a data pattern matching the last serial data item register is read from the SROM default value 0xffffffff An 8 Kbyte EEPROM is provided onboard for this us...

Page 38: ... Multiple MV64360 Support 0 Not supported 1 Supported AD 12 Resistor 1 PCI_0 Pads Calibration 0 Calibration Disabled 1 Calibration Enabled AD 13 Resistor 1 PCI_1 Pads Calibration 0 Calibration Disabled 1 Calibration Enabled AD 15 14 Resistors 10 BootCS Device Width 00 8 bits 01 16 bits 10 32 bits 11 Reserved AD 16 Resistor 1 PCI Retry 0 Disable 1 Enable AD 17 Fixed 1 1 Must pull high Table 2 2 MV6...

Page 39: ...RAM clock AD 21 20 Resistors 01 DRAM control path pipeline select 00 Reserved 01 Two Pipe stages 10 Reserved 11 Three pipe stages AD 24 22 Resistors 000 DRAM read path control 000 100 DRAM running in sync mode 001 111 DRAM running in async mode AD 25 Fixed 0 Gigabit port 3 Enable 0 Disable 1 Enable AD 28 26 Resistors 101 PCI_1 DLL control 000 DLL disable 001 Conventional PCI mode at 66MHz 101 PCI ...

Page 40: ...TBD Refer to MV64360 Specification MV S100614 00 Rev B 1 13 2003 page 144 for detail MVME6100 is not using this mode BADR 0 Resistor 1 DRAM PLL NP 1 Pull up NP BADR 1 Resistor 1 DRAM PLL HIKVCO 1 Pull down HIKVCO BADR 2 Resistor 1 DRAM PLL NP 0 PLL power down normal operation 1 PLL power up TxD0 6 1 Resistor X DRAM PLL M Divider TBD Refer to MV64360 Specification MV S100614 00 Rev B 1 13 2003 page...

Page 41: ...ps The boot device bank is the same as any of the other device banks except that its default address map matches the PowerPC CPU boot address 0xfff0 0100 and that its default width is sampled at reset Real Time Clock and NVRAM The Real Time Clock NVRAM Watchdog Timer is implemented using a SGS Thompson M48T37V Timekeeper SRAM and M4T28 BR12SH1 SnapHat battery Refer to the M48T37V data sheets for a...

Page 42: ...l EEPROM following a reset and initialize any number of internal registers In the second function the controller is used by the system software to read the contents of the VPD and SPD EEPROMs contained on the MVME6100 to initialize the memory controller and other interfaces For additional details regarding the MV64360 two wire serial controller operation refer to the MV64360 System Controller Data...

Page 43: ...ce Detect There are two onboard SPD serial EEPROMs on the MVME6100 accessible via the I2C serial interface The first 128 bytes of each SPD contains module type SDRAM organization and timing parameters Table 2 4 I2C Bus Device Addressing Device Function Size Device Address A2A1A0 I2C BUS Address Notes Memory SPD Bank 0 and 1 256 x 8 000b A0 1 Memory SPD Bank 2 and 3 256 x 8 001b A2 1 Reserved PMCSp...

Page 44: ...vided for user MV64360 initialization VPD and User Configuration EEPROMs The MVME6100 board contains an Atmel AT24C64 or compatible Vital Product Data VPD EEPROM containing configuration information specific to the board Typical information that may be present in the VPD is manufacturer board revision build version date of assembly memory present options present and L3 cache information A second A...

Page 45: ...d the PMC Slots PCI Mode Frequency Selection The MVME6100 PCI Bus 0 bus is be set to PCI X and 133 MHz for maximum performance Onboard logic drives the PCI X initialization pattern as defined by the PCI X Addendum to the PCI Local Bus Specification Revision 1 0a at the rising edge of RST The MVME6100 dynamically determines the mode and frequency of the PCI Bus 1 defined by the PCI X Addendum to th...

Page 46: ... Both sites should be set for the same VIO that is keyed identically If 5V VIO is selected PCI Bus 1 reverts to PCI mode at 33 MHz PCI Configuration Space The MV64360 controls all PCI configuration space access from either the CPU or PCI busses The IDSEL assignments for MVME6100 are shown on the following table Table 2 6 IDSEL Mapping for PCI Devices PCI Bus Device Number Field PCI Address Line ID...

Page 47: ...onfigure the MPP pins to function as request grant pairs for the internal PCI arbiter The arbitration assignments on MVME6100 are as follows PCI Bus 1 Local Bus PMC Expansion Slots Two PMC slots reside on the PCI Bus 1 local bus The presence of PMCs can be positively determined by reading System Status Register 3 The INTA INTB INTC and INTD from the PMC slots are routed by the MVME6100 as follows ...

Page 48: ...s the VMEchip2 and Universe it includes new features and enhancements Therefore Tsi148 is not register compatible with the VMEchip2 or Universe chips See the Tsi148 User s Manual from Tundra Semiconductor listed in Appendix A Related Documentation for further details PCI6520 PMCSpan Bridge The PMCSpan interface is provided by the PCI6520 PCI6520 is a PCI X to PCI X transparent bridge to interface ...

Page 49: ...ward compatible with the Discovery I implementation since the registers are placed at different offsets The external interrupt sources will use the GPP interface to register external interrupts The following table shows the MVME6100 interrupt assignment to MV64360 GPP pins Table 2 8 MV64360 Interrupt Assignments GPP Group MV64360 Edge Level Polarity Interrupt Source Notes 0 GPP 0 Level High COM1 C...

Page 50: ...INTB 2 GPP 20 Level Low PCI VME INT 0 Tsi148 LINT0 PMCspan INT 2 1 5 GPP 21 Level Low PCI VME INT 1 Tsi148 LINT1 PMCspan INT 3 1 5 GPP 22 Level Low PCI VME INT 2 Tsi148 LINT2 PMCspan INT 0 1 5 GPP 23 Level Low PCI VME INT 3 Tsi148 LINT3 PMCspan INT 1 1 5 3 GPP 24 Reserved for SROM initialization active InitAct output GPP 25 Reserved for Watchdog Timer WDE output GPP 26 Reserved for Watchdog Timer ...

Page 51: ... 7 GPP 1 4 30 31 are unused They are resistively pulled high onboard MV64360 Endian Issues The MV64360 supports only a big endian CPU bus The endianess of the local memory DDR and SRAM is also big endian Data transferred to from the local memory is never swapped The internal registers of the MV64360 are always programed in little endian On a CPU access to the internal registers data is byte swappe...

Page 52: ...eb literature site http www motorola com computer literature To obtain the most up to date product information in PDF or HTML format visit http www motorola com computer literature Table A 1 Motorola Computer Group Documents Document Title Motorola Publication Number MVME6100 Single Board Computer Installation and Use V6100A IH MOTLoad Firmware Package User s Manual MOTLODA UM IPMC712 761 I O Modu...

Page 53: ...03 675 2150 Web Site http e www motorola com webapp sps library prod_lib jsp E mail ldcformotorola hibbertco com MPC7457EC D Rev 1 3 3 2003 Tsi148 PCI X to VME Bus Bridge User Manual Tundra Semiconductor Corporation 603 March Road Ottawa Ontario Canada K2K 2M5 Web Site www tundra com 80A3020_MA001_02 PowerPC Apollo Microprocessor Implementation Definition Book IV Literature Distribution Center for...

Page 54: ...11 8141 Web Site http developer intel com design flcomp datashts 290737 htm 290737 PCI6520 HB7 Transparent PCIx PCIx Bridge Preliminary Data Book PLX Technology Inc 870 Maude Avenue Sunnyvale California 94085 Web Site http www hintcorp com products hint default asp PCI6520 Ver 0 992 EXAR ST16C554 554D ST68C554 Quad UART with 16 Byte FIFOs EXAR Corporation 48720 Kato Road Fremont CA 94538 Web Site ...

Page 55: ...M48T37V 2 Wire Serial CMOS EEPROM Atmel Corporation San Jose CA Web Site http www atmel com atmel support AT24C02N AT24C64A Dallas Semiconductor DS1621Digital Thermometer and Thermostat Dallas Semiconductor Web Site http www dalsemi com DS1621 TSOP Type I Shielded Metal Cover SMT Yamaichi Electronics USA Web Site http www yeu com Table A 2 Manufacturers Documents continued Document Title and Sourc...

Page 56: ...rce Publication Number VITA http www vita com VME64 Specification ANSI VITA 1 1994 VME64 Extensions ANSI VITA 1 1 1997 2eSST Source Synchronous Transfer VITA 1 5 199x PCI Special Interest Group PCI SIG http www pcisig com Peripheral Component Interconnect PCI Local Bus Specification Revision 2 0 2 1 2 2 PCI Local Bus Specification PCI X Addendum to the PCI Local Bus Specification Rev 1 0b IEEE htt...

Page 57: ...1 9 MOTLoad s PCI memory map 1 9 MOTLoad s processor memory map 1 7 N NVRAM 2 8 P presence detect register 1 16 R real time clock 2 8 registers config switch register 1 17 presence detect register 1 16 system status register 1 1 11 system status register 2 1 13 system status register 3 1 15 time base enable register 1 19 related documentation A 1 S suggestions submitting xiv system I O memory map ...

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