Architecture
388
SPRUH82C – April 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
DDR2/mDDR Memory Controller
The DDR2/mDDR memory controller may now have a final read and write command. If the Read FIFO is
not full, then the read command will be performed before the write command, otherwise the write
command will be performed first.
Besides commands received from on-chip resources, the DDR2/mDDR memory controller also issues
refresh commands. The DDR2/mDDR memory controller attempts to delay refresh commands as long as
possible to maximize performance while meeting the SDRAM refresh requirements. As the DDR2/mDDR
memory controller issues read, write, and refresh commands to DDR2/mDDR SDRAM memory, it adheres
to the following rules:
1. Refresh request resulting from the Refresh Must level of urgency being reached
2. Read request without a higher priority write (selected from above reordering algorithm)
3. Refresh request resulting from the Refresh Need level of urgency being reached
4. Write request (selected from above reordering algorithm)
5. Refresh request resulting from Refresh May level of urgency being reached
6. Request to enter self-refresh mode
The following results from the above scheduling algorithm:
•
All writes from a single master will complete in order
•
All reads from a single master will complete in order
•
From the same master, any read to the same location (or within 2048 bytes) as a previous write will
complete in order
14.2.6.2 Command Starvation
The reordering and scheduling rules listed above may lead to command starvation, which is the
prevention of certain commands from being processed by the DDR2/mDDR memory controller. Command
starvation results from the following conditions:
•
A continuous stream of high-priority read commands can block a low-priority write command
•
A continuous stream of DDR2/mDDR SDRAM commands to a row in an open bank can block
commands to the closed row in the same bank.
To avoid these conditions, the DDR2/mDDR memory controller can momentarily raises the priority of the
oldest command in the command FIFO after a set number of transfers have been made. The
PR_OLD_COUNT bit in the peripheral bus burst priority register (PBBPR) sets the number of the transfers
that must be made before the DDR2/mDDR memory controller will raise the priority of the oldest
command.
14.2.6.3 Possible Race Condition
A race condition may exist when certain masters write data to the DDR2/mDDR memory controller. For
example, if master A passes a software message via a buffer in DDR2/mDDR memory and does not wait
for indication that the write completes, when master B attempts to read the software message it may read
stale data and therefore receive an incorrect message. In order to confirm that a write from master A has
landed before a read from master B is performed, master A must wait for the write completion status from
the DDR2/mDDR memory controller before indicating to master B that the data is ready to be read. If
master A does not wait for indication that a write is complete, it must perform the following workaround:
1. Perform the required write.
2. Perform a dummy write to the DDR2/mDDR memory controller SDRAM status register.
3. Perform a dummy read to the DDR2/mDDR memory controller SDRAM status register.
4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The
completion of the read in step 3 ensures that the previous write was done.
The EDMA peripheral does not need to implement the above workaround. The above workaround is
required for all other peripherals. See your device-specific data manual for more information.
