Texas Instruments AM1808, Technical Reference Manual

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Registers
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1262 SPRUH82C – April 2013 – Revised September 2016
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Multichannel Buffered Serial Port (McBSP)
25.3.12 Write FIFO Control Register (WFIFOCTL)
The Write FIFO control register (WFIFOCTL) is shown in Figure 25-53 and described in Table 25-36 .
NOTE: The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO. If the
Write FIFO is to be enabled, it must be enabled prior to taking the McBSP out of reset.
Figure 25-53. Write FIFO Control Register (WFIFOCTL)
31 17 16
Reserved WENA
R-0 R/W-0
15 8 7 0
WNUMEVT WNUMDMA
R/W-10h R/W-4h
LEGEND: R = Read only; R/W = Rear/Write; - n = value after reset
Table 25-36. Write FIFO Control Register (WFIFOCTL) Field Descriptions
Bit Field Value Description
31-17 Reserved 0 Reserved
16 WENA Write FIFO enable bit.
0 Write FIFO is disabled. The WLVL bit in the Write FIFO status register (WFIFOSTS) is reset to 0
and the pointers are initialized, that is, the Write FIFO is “flushed.”
1 Write FIFO is enabled. If the Write FIFO is to be enabled, it must be enabled prior to taking the
McBSP out of reset.
15-8 WNUMEVT 0-FFh Write word count per DMA event (32-bit). When the Write FIFO has space for at least WNUMEVT
words of data, then an XEVT (transmit DMA event) is generated to the host/DMA controller. This
value must be set prior to enabling the Write FIFO.
0 0 words
1h 1 word
2h 2 words
... ...
40h 64 words
41h-FFh Reserved
7-0 WNUMDMA 0-FFh Write word count per transfer (32-bit words). Upon a transmit DMA event from the McBSP,
WNUMDMA words are transferred from the Write FIFO to the McBSP. This value must be set prior
to enabling the Write FIFO.
0 0 words
1 1 word
2h-FFh Reserved