Circuit Description
4
2
Circuit Description
The schematic diagrams for the EVM are located at the end of this document
(see Figure 2, Figure 3, and Figure 4).
2.1
Analog Inputs
The EVM can be configured to provide the AFE with transformer-coupled in-
puts from a single-ended source. The inputs are provided via SMA connectors
(J6) for a transformer-coupled input.
2.2
Clock Inputs
The initial configuration of the EVM provides a transformer-coupled clock input
(J8) to the AFE differential clock.
2.3
Serial Interface
The EVM has a USB interface input through FPGA to control a serial bus to
operate of the registers of the AFE.
2.4
Outputs
The data outputs from the AFE have two possible connection options: two
40-pin connectors (P3 and P4), or two DSK 80-pin connectors (P1 and P5).
-
40-pin connector output pins:
J
I Output: on connector P3 (Digital Interface 1), from pin 4 (LSB) to pin
34 (MSB), even pins only (odd pins are ground).
J
Q output: on connector P4 (Digital Interface 2), from pin 2 (LSB) to pin
32 (MSB), even pins only (odd pins are ground).
J
Strobe: On connector P3, pin 2 (sample I and Q data on falling edge of
strobe)
-
80-pin connector output pins:
J
See schematic diagrams shown in Figure 2, Figure 3, and Figure 4.
Summary of Contents for AFEDRI8201EVM
Page 1: ...August 2005 User s Guide SBAU099B High Speed Communications...
Page 15: ...Physical Description 9 AFEDRI8201EVM Figure 2 Schematic AFEDRI8201...
Page 16: ...Physical Description 10 Figure 3 Schematic Xilinx...
Page 17: ...Physical Description 11 AFEDRI8201EVM Figure 4 Schematic Power Supply...
Page 18: ...Physical Description 12 Figure 5 PCB Layout Top Layer top view...
Page 19: ...Physical Description 13 AFEDRI8201EVM Figure 6 PCB Layout Ground Plane top view...
Page 20: ...Physical Description 14 Figure 7 PCB Layout Power Plane top view...
Page 21: ...Physical Description 15 AFEDRI8201EVM Figure 8 PCB Layout Bottom Layer bottom view...