Operation
15
SBAU315A – July 2018 – Revised June 2019
Copyright © 2018–2019, Texas Instruments Incorporated
ADS9224REVM-PDK
Specify a target SCLK frequency (in Hz), and the GUI tries to match this frequency as closely as possible
by changing the PHI PLL settings. However, the achievable frequency may differ from the target value
entered. Similarly, the sampling rate of the ADC can be adjusted by modifying the
Target Sampling Rate
argument (also in Hz). The achievable ADC sampling rate can differ from the target value depending on
the applied SCLK frequency and selected
Device Mode
. The closest achievable match is then displayed.
Thus, this pane allows the user to test various available settings on the ADS9224R in an iterative fashion
until the best settings for the corresponding test scenario are found.
The
Device Reset
button functions as a master reset to both the ADS9224REVM and the GUI. When the
button is pressed, the ADC resets to the reset configuration explained in the
. The
GUI also updates the interface configuration settings and the register map to reflect the device reset state.
6.2
Register Map Configuration Tool
Use the register map configuration tool to view and modify the registers of the ADS9224R. To select this
tool, click on the
Register Map Config
radio button in the
Pages
section at the top of the left pane, as
shown in
. At power-up, the values on this page correspond to the host configuration settings
that enable ADC sampling at the maximum sampling rate specified for the ADC. Edit the register values
by double-clicking the corresponding value field. If interface mode settings are affected by the change in
register values, this change reflects on the left pane immediately. The effect of changes in the register
value reflect on the ADS9224R device on ADS9224REVM-PDK based on the
Update Mode
selection, as
described in
.
Figure 11. Register Map Configuration