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Texas Instruments ADS9218EVM-PDK User Manual Download Page 21

Figure 7-2

 shows the boost converters and the low-dropout regulators for internal and external power 

connections.

1  

2  

J17  

GND  

OUT  

5  

GND  

2  

IN

1  

EN

3  

NC

4  

TPS7A2050PDBVR

U3

5V

GND  

1µF  
16V  

C1

1µF  
16V  

C2

GND  

GND  

IN

1  

GND  

2  

CE

3  

N/C  

4  

ST

5  

OUT  

6  

LM66100DCKR  

U2

GND  

1V8_VDD  

GND  

1µF  
16V  

C3

1µF  
16V  

C4

GND  

GND  

AVDD

VDD  

EN

3  

IN

1  

NC

4  

OUT  

5  

GND  

2  

TPS7A2018PDBVR

U4

SW

1  

GND  

2  

EN

3  

FB

4  

VOUT

5  

VBAT

6  

TPS61070DDCR

U5

10uH

L1

GND  

16V  

10uF

C5

GND  

1.96M 

R2

200k

R3

GND  

GND  

SPRW_SUP_3P3

LDO_IN

6V

D1

GND  

1  

2  

3  

J18  

10V  
1µF  

C32  

GND  

16V  

10uF

C6

2.2k

R1

Green  

1  

2  

D2

GND  

Figure 7-2. ADS9218EVM Power Section

www.ti.com

Bill of Materials, Schematics, and Layout

SBAU409 – SEPTEMBER 2022

Submit Document Feedback

ADS9218EVM-PDK Evaluation Module

21

Copyright © 2022 Texas Instruments Incorporated

Summary of Contents for ADS9218EVM-PDK

Page 1: ...ed circuit board PCB that facilitates connection to a standard FPGA mezzanine card FMC connecter used in many field programmable gate array FPGA kits The EVM PDK eases the evaluation of the ADS9218 de...

Page 2: ...tic 6 Figure 2 3 Common Mode Amplifier Drive 7 Figure 2 4 Voltage Reference 7 Figure 3 1 FMC Connector Signals Definition 8 Figure 3 2 Clock Connection 9 Figure 4 1 Boost Converter LDO and Input Polar...

Page 3: ...on of the ADS9218 ADC The FMC connecter adapter board facilitates connection to common FPGA kits The TSWDC155EVM controller sold separately requires a separate 5 V 2 A power source the ADS9218EVM requ...

Page 4: ...4 096 V voltage reference onboard ultra low noise low dropout LDO regulators for 5 0 V analog supply and 1 8 V for the digital supply Subminiature version A SMA connections for external clock or clock...

Page 5: ...TM_B 25 DOUTP_A 28 DOUTP_B 26 CS 17 PWDN 22 RESET 21 DCLKIN 31 DCLKM 23 DCLKP 24 FCLKM 29 FCLKP 30 REFIO 39 SCLK 18 SDI 19 SDO 20 SMPL_CLK 32 SPI_EN 16 SYNC 33 Thermal_Pad 41 VCMOUT 5 AGND 2 AGND 9 AG...

Page 6: ...s component selection and can help adjust component values for different optimizations Figure 2 2 shows a schematic of the FDA driver components GND 1 2 3 4 5 J3 GND 1 2 3 4 5 J4 GND GND AINP_A AINM_A...

Page 7: ...35 VCMOUT DNP Figure 2 3 Common Mode Amplifier Drive 2 4 Voltage Reference As shown in Figure 2 4 the REF7040 is a very low drift low noise highly stable 4 096 V reference This reference can externall...

Page 8: ...E11 E11 E12 E12 E13 E13 E14 E14 E15 E15 E16 E16 E17 E17 E18 E18 E19 E19 E20 E20 E21 E21 E22 E22 E23 E23 E24 E24 E25 E25 E26 E26 E27 E27 E28 E28 E29 E29 E30 E30 E31 E31 E32 E32 E33 E33 E34 E34 E35 E35...

Page 9: ...M J5 grounds the negative clock if a single ended clock is applied Figure 3 2 shows the clock connection circuit GND GND 1 2 J5 1 2 3 4 5 J1 GND 1 2 3 4 5 J2 EXT_SMPL_CLKP EXT_SMPL_CLKM 49 9 R4 DNP 1...

Page 10: ...17 In this case U2 an LM66100 device provides reverse polarity protection if the connection is miswired Figure 4 1 shows a schematic for various protection circuits 1 2 J17 GND OUT 5 GND 2 IN 1 EN 3 N...

Page 11: ...the Tools and Software folder of the ADS9218EVM and run the GUI installer to install the EVM GUI software on your computer Accept all the license agreements and choose the destination location projec...

Page 12: ...omputer This process takes a few minutes At completion you can launch a readme text file and the application Figure 5 2 shows these steps Figure 5 2 Installation Process ADS9218EVM Software Installati...

Page 13: ...I as described in Figure 6 2 7 Press the buttons Initialize USB Power Up Program FPGA and Initialize ads98xx on the Config tab to power up and configure the EVM see Figure 6 4 for details 8 Connect a...

Page 14: ...UI from the start menu Figure 6 2 Start the Software GUI EVM Operation www ti com 14 ADS9218EVM PDK Evaluation Module SBAU409 SEPTEMBER 2022 Submit Document Feedback Copyright 2022 Texas Instruments I...

Page 15: ...EVM but can be helpful to configure the EVM more closely to your end application Review the Schematic to understand how these connections are used Clock Source Figure 6 3 Optional Connections www ti c...

Page 16: ...and Program FPGA buttons some status LEDs on the hardware illuminate The power up step takes the longest time approximately 30 seconds After all four buttons are pressed the power on the ADS9218EVM is...

Page 17: ...d THD data Finally select the Hanning type window to eliminate spectral leakage in the FFT result When these changes are made press the Start Capture button to collect time domain and frequency domain...

Page 18: ...RM188C81A106MA7 3D MuRata D1 1 6 V Diode TVS Bi 6 V SMB SMB SMBJ6 0CA Littelfuse D2 1 Green LED Green SMD LED_0805 APT2012LZGCK Kingbright H1 H2 H3 H4 4 Machine Screw Round 4 40 x 1 4 Nylon Philips pa...

Page 19: ...1 300 mA ultra low noise low IQ low dropout LDO linear regulator with high PSRR 5 SOT 23 40 to 125 SOT23 5 TPS7A2050PDBVR Texas Instruments U4 1 Linear Voltage Regulator IC Positive Fixed 1 Output 30...

Page 20: ...AINM_B VCMOUT VCMOUT AINP_A AINM_A 10V 0 1 F C17 GND 5V GND VCMOUT GND 10V 1uF C24 VCM_FDA REFIO 1 2 3 J11 SMPL_CLKP EXT_SMPL_CLKP FPGA_SMPL_CLKP VIN 2 EN 1 OUTF 7 OUTS 6 GND 3 GND 4 GND 5 GND 8 REF7...

Page 21: ...F 16V C4 GND GND AVDD VDD EN 3 IN 1 NC 4 OUT 5 GND 2 TPS7A2018PDBVR U4 SW 1 GND 2 EN 3 FB 4 VOUT 5 VBAT 6 TPS61070DDCR U5 10uH L1 GND 16V 10uF C5 GND 1 96M R2 200k R3 GND GND SPRW_SUP_3P3 LDO_IN 6V D1...

Page 22: ...E34 E35 E35 E36 E36 E37 E37 E38 E38 E39 E39 E40 E40 J27E ASP 134486 01 F1 F1 F2 F2 F3 F3 F4 F4 F5 F5 F6 F6 F7 F7 F8 F8 F9 F9 F10 F10 F11 F11 F12 F12 F13 F13 F14 F14 F15 F15 F16 F16 F17 F17 F18 F18 F19...

Page 23: ...r is shown in red the top overlay in yellow and the bottom layer in blue Figure 7 4 ADS9218EVM Layout www ti com Bill of Materials Schematics and Layout SBAU409 SEPTEMBER 2022 Submit Document Feedback...

Page 24: ...ther than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control tec...

Page 25: ...These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not in...

Page 26: ...instructions set forth by Radio Law of Japan which includes but is not limited to the instructions below with respect to EVMs which for the avoidance of doubt are stated strictly for convenience and s...

Page 27: ...any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electr...

Page 28: ...R DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthe...

Page 29: ...change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of thes...

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