Texas Instruments ADS8568EVM-PDK, User Manual, Page: 7 / 35

3 Digital Interface
As noted in Section 1 , the EVM interfaces with the PHI and communicates with the computer over the USB.
There are two devices on the EVM with which the PHI communicates: the ADS8568 ADC (over SPI) and the
EEPROM (over I2C). The EEPROM comes pre-programmed with the information required to configure and
initialize the ADS8568 platform. When the hardware is initialized, the EEPROM is no longer used.
3.1 Parallel Interface
The parallel interface signals are generated on the PHI controler and connected through J10. Each of these
signals has a 47-Ω resistor between the device and the controler to slow down the signal edges in order to
minimize signal overshoot. The digital signals can be monatored on J11 test header.
3.2 Serial Interface (SPI)
The ADS8568 ADC uses SPI serial communication in mode 2 (CPOL=1 and CPHA=0). Because the serial clock
(SCLK) frequency can be as fast as 45 MHz, the ADS8568EVM offers 47-Ω resistors between the controler
and device to aid with signal integrity. Typically, in high-speed SPI communication, fast signal edges can cause
overshoot; these 47-Ω resistors slow down the signal edges in order to minimize signal overshoot.
3.3 Connections to PHI connector
Connector J10 is used to connect the PHI digital controller PCB to the ADS8568EVM. This connector has all the
digital signals as well as the 5.5V regulated supply and the DVDD supply. The power for the two supplies is from
the USB connection. The 5.5V supply is used to generate the AVDD supply. This connector also provides I2C
signals that are used on the EEPROM identification circuit.
GND GND
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
GND
MP1
GND
MP2
GND
MP3
GND
MP4
J10
QTH-030-01-L-D-A
CONVSTA
CONVSTB
CONVSTC
CONVSTD
~PAR_SER
~STBY
REFEN_~WR
BUSY
ASLEEP
~HW_SW
5.11 R113
EVM_ID_SDA
EVM_ID_SCL
ID_PWR
ID_PWR
GND
GND
DB0_DCIND DB1_DCINC
DB2_DCINB DB3_DCINA
DB4 DB5_SELCD
DB6_SELB DB7
DB8_DCEN DB9_SDI
DB10_SCLK DB11_REFBUFEN
DB12_SDOA DB13_SDOB
DB14_SDOC DB15_SDOD
~RD ~CS_~FS
DVDD
TP2
5.5V
TP1
DVDD
GND
5V
D5
DB0/DCIN_D DB1/DCIN_C
DB2/DCIN_B DB3/DCIN_A
DB4 DB5/SEL_CD
DB6/SEL_B DB7
DB8/DCEN DB9/SDI
DB10/SCLK DB11/REFBUFEN
DB12/SDO_A DB13/SDO_B
DB14/SDO_C DB15/SDO_D
RANGE/XCLK
~RD ~CS/~FS
BUSY
~HW/SW
ASLEEP
REFEN/~WR RESET
~STBY ~PAR/SER
CONVST_A
CONVST_B CONVST_C
CONVST_D
RANGE_XCLK BUSY
~HW_SW
ASLEEP
~STBY
10uF
C61
REFEN_~WR
~PAR_SER
CONVSTA
CONVSTB CONVSTC
CONVSTD
DB0_DCIND
DB1_DCINC
DB2_DCINB
DB3_DCINA
DB4
DB5_SELCD
DB6_SELB
DB7
DB8_DCEN
DB9_SDI
DB10_SCLK
DB11_REFBUFEN
DB12_SDOA
DB13_SDOB
DB14_SDOC
DB15_SDOD
~CS_~FS
~RD
RANGE_XCLK
RET_RD
RET_SCLK
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15
17
19
21
23
25
27
29
31
16
18
20
22
24
26
28
30
32
J11
TSW-116-07-G-D
GND GND
EVM_ID_WP
RESET1
RESET1
Figure 3-1. PHI to ADS8568EVM connector
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SBAU193E – JUNE 2011 – REVISED MAY 2021
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