1
2
3
4
5
6
A
B
C
D
6
5
4
3
2
1
D
C
B
A
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Revision History
REV
ECN Number
Approved
DOCUMENT CONTROL #:
1
3
BlockDiagram.sch
A
DATE:
6-May-2004
ADS8381/ADS8383EVM Block Diagram
6448017
+IN
EXT_REF
B_C
S
B_R
D
B_C
O
N
VST
B_BYTE B_BU
S18/
16
BU
SY
DB
[1
7...0
]
Analog-to-Digital Converter
ADC Data Bus
ADC Control
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
P2
ADC_CS
ADC_RD
ADC_CONVST
BYTE
BUS18/16
B_BUSY
Analog Input
1
2
3
4
5
6
7
8
9 10
11 12
13 14
15 16
17 18
19 20
P1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
P3
+VA
-VA
B_DB[17...0]
DB
[1
7...0
]
A
DC_
CS
A
DC_
RD
A
DC_
CONV
S
T
BYTE BU
S18/
16
B_BU
SY
BU
SY
B_C
S
B_R
D
B_C
O
N
VST
B_BYTE
B_BU
S18/
16
+5VA
+VA
-VA
+BVDD
A0 A1 A2
DC_
CS
INT
c
Power & Digital Buffer
J2
B_DB[17...0]
DB[17..0]
B_DB0
B_DB1
B_DB2
B_DB3
B_DB4
B_DB5
B_DB6
B_DB7
B_DB8
B_DB9
B_DB10
B_DB11
B_DB12
B_DB13
B_DB14
B_DB15
B_DB16
B_DB17
Lijoy Philipose
Lijoy Philipose
DC_CS
A0
A1
A2
TP16
TP14
TP15
TP18
TP19
TP20
1
2
3
4
5
6
7
8
9
10
J1
+VA
-VA
+5VD
AGND
+5VA
ADC Control
1
2
3
4
5
6
7
8
9
11
10
12
J4
DGND
+3.3VD
+5VA
W4
INTc