Texas Instruments ADS8350EVM-PDK, User Manual

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ADS8350
AINM-A (Pin 16)
AINP-A (Pin 15)
AINM-B (Pin 5)
AINP-B (Pin 6)
OPA836
Inverting Configuration
SMA J1
Header JP1.2
AIN_A
OPA836 Buffer
V
ref_A
SMA J2
Header JP2.2
AIN_B
JP7
+
AVDD
V
CM
JP8
OPA836
Inverting Configuration
+
AVDD
V
CM
OPA836 Buffer
V
ref_B
EVM Analog Interface
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Figure 1. ADS8350EVM Analog Interface Input Connections
Table 1 summarizes the JP1 and JP2 analog interface connectors.
Table 1. JP1 and JP2: Analog Interface Connections
Terminal Number Signal Description
Channel A inverted input. The signal is routed through an
JP1.2 AIN_A
OPA836 in the inverting configuration.
Channel B inverted input. The signal is routed through an
JP2.2 AIN_B
OPA836 in the inverting configuration.
Table 2 lists the SMA analog inputs.
Table 2. SMA Analog Interface Connections
Terminal Number Signal Description
Channel A inverted input. The signal is routed through an
J1 AIN_A
OPA836 in the inverting configuration.
Channel B inverted input. The signal is routed through an
J2 AIN_B
OPA836 in the inverting configuration.
4 ADS8350EVM-PDK SBAU218A – April 2014 – Revised October 2014
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